2010/8/5 Idwer Vollering <vidwer@gmail.com>
2010/8/3 Myles Watson <mylesgw@gmail.com>
On Tue, Aug 3, 2010 at 10:59 AM, Idwer Vollering <vidwer@gmail.com> wrote:

> My problem is two-fold:
> 1) Running the patched qemu segfaults.
> $ sudo ./i386-softmmu/qemu -serialice /dev/ttyUSB0 -hda /dev/zero -L bios/
> [sudo] password for idwer:
> SerialICE: Open connection to target hardware...
> SerialICE: Waiting for handshake with target... target alife!
try the latest qemu in the SerialICE tree


It's already patched, and it has been updated more recently than the patch.

> 2) Right now, the serialice shell appears only once: after flashing
> serialice.rom and performing a soft reset from vendor bios to serialice.
> SerialICE v1.5 (Aug  3 2010)

Following quote is after soft reset, typing some text and hitting the reset button:

SerialICE v1.5 (Aug 27 2010)

> 1
> 2
> 3
> 4
> 5
> 6
> 7
> 8
> 9
> 0
> r
> e
> s
> e
> t
> -
> -
> >
> òóñôõöôöòñðôõô÷ôôöðôÿôõõôõôô

Sounds like SerialICE is depending on some initialization from the
vendor BIOS.  I guess an ugly way to test it would be to copy the
working configuration bits from lspci and hard code them into
SerialICE until you find what's wrong.

Since the southbridge and superio datasheets mention the existence of two serial ports, I followed their guidance.
I thought that (the console printing part of) SerialICE, when setup the correct way, should survive a hard reset/power cycle regardless of the qemu part is running or not.

Since I don't have an oscilloscope, I've tried setting CLKSEL to 24 MHz and 48 MHz:
pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xb4); // 24 MHz and KBC=1
pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc4); // 48 MHz and KBC=1

What information is leading, the info from the superio or the info from the southbridge ?

Attached the mainboard code as well.

Attaching .config, dmesg, lspci and the patch against svn.