Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1189
-gerrit
commit 773e0c310e3236729cb161dce17decdd9119625a Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat May 19 12:31:10 2012 +0300
SerialICE: Add support for Intel D845GBV2
This is my test platform for booting SerialICE from PCI add-on card. This ancient mainboard has soldered PLCC32 and FWH write-protection lock set by vendor BIOS.
Change-Id: I0df0a70bdb721e571561446e7b4e8915aa36f222 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- SerialICE/Kconfig | 4 ++ SerialICE/mainboard/intel_d845gbv2.c | 59 ++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 9844b4a..7199453 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -108,6 +108,9 @@ config BOARD_AOPEN_DXPL_PLUS config BOARD_VIA_EPIA_M850 bool "VIA EPIA M850"
+config BOARD_INTEL_D845GBV2 + bool "Intel D845GBV2" + endchoice
config BOARD_INIT @@ -136,6 +139,7 @@ config BOARD_INIT default "asus_p4p800-vm.c" if BOARD_ASUS_P4P800_VM default "aopen_dxpl-plus.c" if BOARD_AOPEN_DXPL_PLUS default "via_epia_m850.c" if BOARD_VIA_EPIA_M850 + default "intel_d845gbv2.c" if BOARD_INTEL_D845GBV2
config SOUTHBRIDGE_INIT string diff --git a/SerialICE/mainboard/intel_d845gbv2.c b/SerialICE/mainboard/intel_d845gbv2.c new file mode 100644 index 0000000..3588c33 --- /dev/null +++ b/SerialICE/mainboard/intel_d845gbv2.c @@ -0,0 +1,59 @@ +/* + * SerialICE + * + * Copyright (C) 2012 Kyösti Mälkki kyosti.malkki@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Intel D845GBV2 "; + +#define SUPERIO_CONFIG_PORT 0x2e + +/* Hardware specific functions */ +static void southbridge_init(void) +{ + /* Set NO_REBOOT flag */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xd4), 0x02); + + /* Select COM1 COM2 I/O ranges. */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xe0), 0x10); + + /* Enable COM1, COM2, KBD, SIO config registers 0x2e. */ + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0xe6), 0x1403); + + /* Enable Serial IRQ */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); +} + +static void superio_init(void) +{ + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + + /* Settings for LPC47M172 with LD_NUM = 0. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 3); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); +} + +static void chipset_init(void) +{ + southbridge_init(); + superio_init(); +} +