pci_bios_alloc() can be used to allocate space in the PCI region for other purposes. This is needed by the AMD IOMMU support code.
Signed-off-by: Eduard - Gabriel Munteanu eduard.munteanu@linux360.ro --- src/pciinit.c | 17 +++++++++++++---- 1 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/pciinit.c b/src/pciinit.c index 0556ee2..bfc669f 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -75,6 +75,16 @@ static void pci_bios_init_bridges(u16 bdf) } }
+static inline u32 pci_bios_alloc(u32 *region, u32 size) +{ + u32 ret; + + ret = ALIGN(*region, size); + *region = ret + size; + + return ret; +} + static void pci_bios_init_device(u16 bdf) { int class; @@ -146,14 +156,13 @@ static void pci_bios_init_device(u16 bdf) pci_config_writel(bdf, ofs, old);
if (val != 0) { - u32 size = (~(val & mask)) + 1; + u32 base, size = (~(val & mask)) + 1; if (val & PCI_BASE_ADDRESS_SPACE_IO) paddr = &pci_bios_io_addr; else paddr = &pci_bios_mem_addr; - *paddr = ALIGN(*paddr, size); - pci_set_io_region_addr(bdf, i, *paddr); - *paddr += size; + base = pci_bios_alloc(paddr, size); + pci_set_io_region_addr(bdf, i, base); } } break;
This initializes the AMD IOMMU and creates ACPI tables for it.
Signed-off-by: Eduard - Gabriel Munteanu eduard.munteanu@linux360.ro --- Makefile | 2 +- src/acpi.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/iommu.c | 64 +++++++++++++++++++++++++++++++++++++++++++++ src/iommu.h | 12 ++++++++ src/pci.h | 4 +++ src/pci_ids.h | 1 + src/pci_regs.h | 1 + src/pciinit.c | 11 ++++++++ 8 files changed, 173 insertions(+), 1 deletions(-) create mode 100644 src/iommu.c create mode 100644 src/iommu.h
diff --git a/Makefile b/Makefile index fe0c1ce..98f253d 100644 --- a/Makefile +++ b/Makefile @@ -14,7 +14,7 @@ OUT=out/ SRCBOTH=misc.c pmm.c stacks.c output.c util.c block.c floppy.c ata.c mouse.c \ kbd.c pci.c serial.c clock.c pic.c cdrom.c ps2port.c smp.c resume.c \ pnpbios.c pirtable.c vgahooks.c ramdisk.c pcibios.c blockcmd.c \ - usb.c usb-uhci.c usb-ohci.c usb-ehci.c usb-hid.c usb-msc.c + usb.c usb-uhci.c usb-ohci.c usb-ehci.c usb-hid.c usb-msc.c iommu.c SRC16=$(SRCBOTH) system.c disk.c apm.c font.c SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \ acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \ diff --git a/src/acpi.c b/src/acpi.c index 0559443..7ea9c55 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -6,6 +6,7 @@ // This file may be distributed under the terms of the GNU LGPLv3 license.
#include "acpi.h" // struct rsdp_descriptor +#include "iommu.h" #include "util.h" // memcpy #include "pci.h" // pci_find_device #include "biosvar.h" // GET_EBDA @@ -268,6 +269,36 @@ struct srat_memory_affinity u32 reserved3[2]; } PACKED;
+/* + * IVRS (I/O Virtualization Reporting Structure) table. + * + * Describes the AMD IOMMU, as per: + * "AMD I/O Virtualization Technology (IOMMU) Specification", rev 1.26 + */ + +struct ivrs_ivhd +{ + u8 type; + u8 flags; + u16 length; + u16 devid; + u16 capab_off; + u32 iommu_base_low; + u32 iommu_base_high; + u16 pci_seg_group; + u16 iommu_info; + u32 reserved; + u8 entry[0]; +} PACKED; + +struct ivrs_table +{ + ACPI_TABLE_HEADER_DEF /* ACPI common table header. */ + u32 iv_info; + u32 reserved[2]; + struct ivrs_ivhd ivhd; +} PACKED; + #include "acpi-dsdt.hex"
static inline u16 cpu_to_le16(u16 x) @@ -599,6 +630,53 @@ build_srat(void) return srat; }
+#define IVRS_SIGNATURE 0x53525649 // IVRS +#define IVRS_MAX_DEVS 32 +static void * +build_ivrs(void) +{ + int iommu_bdf, bdf, max, i; + struct ivrs_table *ivrs; + struct ivrs_ivhd *ivhd; + + iommu_bdf = pci_find_class(PCI_CLASS_SYSTEM_IOMMU); + if (iommu_bdf < 0) + return NULL; + + ivrs = malloc_high(sizeof(struct ivrs_table) + 4 * IVRS_MAX_DEVS); + ivrs->iv_info = iommu_get_misc() & ~0x000F; + + ivhd = &ivrs->ivhd; + ivhd->type = 0x10; + ivhd->flags = 0; + ivhd->length = sizeof(struct ivrs_ivhd); + ivhd->devid = iommu_get_bdf(); + ivhd->capab_off = iommu_get_cap_offset(); + ivhd->iommu_base_low = iommu_get_base(); + ivhd->iommu_base_high = 0; + ivhd->pci_seg_group = 0; + ivhd->iommu_info = 0; + ivhd->reserved = 0; + + i = 0; + foreachpci(bdf, max) { + if (bdf == ivhd->devid) + continue; + ivhd->entry[4 * i + 0] = 2; + ivhd->entry[4 * i + 1] = bdf & 0xFF; + ivhd->entry[4 * i + 2] = (bdf >> 8) & 0xFF; + ivhd->entry[4 * i + 3] = ~(1 << 3); + ivhd->length += 4; + if (++i >= IVRS_MAX_DEVS) + break; + } + + build_header((void *) ivrs, IVRS_SIGNATURE, + sizeof(struct ivrs_table) + 4 * i, 1); + + return ivrs; +} + struct rsdp_descriptor *RsdpAddr;
#define MAX_ACPI_TABLES 20 @@ -639,6 +717,7 @@ acpi_bios_init(void) ACPI_INIT_TABLE(build_madt()); ACPI_INIT_TABLE(build_hpet()); ACPI_INIT_TABLE(build_srat()); + ACPI_INIT_TABLE(build_ivrs());
u16 i, external_tables = qemu_cfg_acpi_additional_tables();
diff --git a/src/iommu.c b/src/iommu.c new file mode 100644 index 0000000..97af24a --- /dev/null +++ b/src/iommu.c @@ -0,0 +1,64 @@ +// AMD IOMMU initialization code. +// +// Copyright (C) 2010 Eduard - Gabriel Munteanu eduard.munteanu@linux360.ro +// +// This file may be distributed under the terms of the GNU LGPLv3 license. + +#include "iommu.h" +#include "pci.h" +#include "types.h" + +#define IOMMU_CAP_BAR_LOW 0x04 +#define IOMMU_CAP_BAR_HIGH 0x08 +#define IOMMU_CAP_RANGE 0x0C +#define IOMMU_CAP_MISC 0x10 + +static int iommu_bdf = -1; +static u8 iommu_cap_offset; +static u32 iommu_base; + +void iommu_init(int bdf, u32 base) +{ + u8 ptr, cap, type; + + /* Only one IOMMU is supported. */ + if (iommu_bdf >= 0) + return; + + foreachcap(bdf, ptr, cap) { + type = pci_config_readb(bdf, cap); + if (type == PCI_CAP_ID_SEC) + break; + } + if (!cap) + return; + + pci_config_writel(bdf, cap + IOMMU_CAP_RANGE, 0); + pci_config_writel(bdf, cap + IOMMU_CAP_BAR_HIGH, 0); + pci_config_writel(bdf, cap + IOMMU_CAP_BAR_LOW, base | 1); + + iommu_bdf = bdf; + iommu_cap_offset = cap; + iommu_base = base; +} + +int iommu_get_bdf(void) +{ + return iommu_bdf; +} + +u8 iommu_get_cap_offset(void) +{ + return iommu_cap_offset; +} + +u32 iommu_get_misc(void) +{ + return pci_config_readw(iommu_bdf, iommu_cap_offset + IOMMU_CAP_MISC + 2); +} + +u32 iommu_get_base(void) +{ + return iommu_base; +} + diff --git a/src/iommu.h b/src/iommu.h new file mode 100644 index 0000000..105af25 --- /dev/null +++ b/src/iommu.h @@ -0,0 +1,12 @@ +#ifndef __IOMMU_H +#define __IOMMU_H + +#include "types.h" + +void iommu_init(int bdf, u32 base); +int iommu_get_bdf(void); +u8 iommu_get_cap_offset(void); +u32 iommu_get_misc(void); + +#endif + diff --git a/src/pci.h b/src/pci.h index eea5b09..3f38a0e 100644 --- a/src/pci.h +++ b/src/pci.h @@ -39,6 +39,10 @@ int pci_next(int bdf, int *pmax); for (MAX=0x0100, BDF=pci_next(0, &MAX) \ ; BDF >= 0 \ ; BDF=pci_next(BDF+1, &MAX)) +#define foreachcap(BDF, PTR, CAP) \ + for (PTR = PCI_CAPABILITY_LIST, CAP = pci_config_readb(BDF, PTR); \ + CAP; \ + PTR = CAP + PCI_CAP_LIST_NEXT, CAP = pci_config_readb(BDF, PTR))
// pirtable.c void create_pirtable(void); diff --git a/src/pci_ids.h b/src/pci_ids.h index 1800f1d..3c695b2 100644 --- a/src/pci_ids.h +++ b/src/pci_ids.h @@ -72,6 +72,7 @@ #define PCI_CLASS_SYSTEM_RTC 0x0803 #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 #define PCI_CLASS_SYSTEM_SDHCI 0x0805 +#define PCI_CLASS_SYSTEM_IOMMU 0x0806 #define PCI_CLASS_SYSTEM_OTHER 0x0880
#define PCI_BASE_CLASS_INPUT 0x09 diff --git a/src/pci_regs.h b/src/pci_regs.h index e5effd4..600df4d 100644 --- a/src/pci_regs.h +++ b/src/pci_regs.h @@ -208,6 +208,7 @@ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ +#define PCI_CAP_ID_SEC 0x0F /* Secure Device (AMD IOMMU) */ #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ diff --git a/src/pciinit.c b/src/pciinit.c index bfc669f..cad9114 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -85,6 +85,14 @@ static inline u32 pci_bios_alloc(u32 *region, u32 size) return ret; }
+static void pci_bios_init_iommu(u16 bdf) +{ + u32 base; + + base = pci_bios_alloc(&pci_bios_mem_addr, 0x4000); + iommu_init(bdf, base); +} + static void pci_bios_init_device(u16 bdf) { int class; @@ -130,6 +138,9 @@ static void pci_bios_init_device(u16 bdf) pci_set_io_region_addr(bdf, 0, 0x80800000); } break; + case PCI_CLASS_SYSTEM_IOMMU: + pci_bios_init_iommu(bdf); + break; default: default_map: /* default memory mappings */
On Sun, Aug 15, 2010 at 10:57:27PM +0300, Eduard - Gabriel Munteanu wrote:
This initializes the AMD IOMMU and creates ACPI tables for it.
Signed-off-by: Eduard - Gabriel Munteanu eduard.munteanu@linux360.ro
There's some questions with how best to create ACPI tables in SeaBIOS/qemu. Can you separate the iommu init code from the acpi tables code?
Thanks, -Kevin
-
Eduard - Gabriel Munteanu -
Kevin O'Connor