Introduce standard wrappers for accessing the VGA IO ports. The VGA ports are pretty bizarre - using wrappers makes the code easier to understand.
-Kevin
Kevin O'Connor (5): vgabios: Add wrapper functions for accessing standard VGA registers. vgabios: Use standard VGA IO wrapper functions in stdvga.c. vgabios: Use standard VGA IO wrapper functions in bochsvga. vgabios: Use standard VGA IO wrappers in clext.c. vgabios: Use standard VGA IO wrappers in geodevga.c.
Makefile | 7 +- vgasrc/bochsvga.c | 53 +++----- vgasrc/bochsvga.h | 2 +- vgasrc/clext.c | 125 ++++++----------- vgasrc/geodevga.c | 19 +-- vgasrc/stdvga.c | 408 +++++++++++++---------------------------------------- vgasrc/stdvga.h | 31 +++- vgasrc/stdvgaio.c | 185 ++++++++++++++++++++++++ vgasrc/vgabios.c | 16 +- 9 files changed, 389 insertions(+), 457 deletions(-) create mode 100644 vgasrc/stdvgaio.c
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- Makefile | 7 +- vgasrc/clext.c | 8 +- vgasrc/stdvga.c | 92 +++------------------------ vgasrc/stdvga.h | 31 +++++++-- vgasrc/stdvgaio.c | 185 +++++++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/vgabios.c | 16 ++-- 6 files changed, 233 insertions(+), 106 deletions(-) create mode 100644 vgasrc/stdvgaio.c
diff --git a/Makefile b/Makefile index c97ed8f..31eb2f9 100644 --- a/Makefile +++ b/Makefile @@ -169,9 +169,10 @@ $(OUT)bios.bin.elf $(OUT)bios.bin: $(OUT)rom.o tools/checkrom.py ################ VGA build rules
# VGA src files -SRCVGA=src/output.c src/util.c src/pci.c vgasrc/vgabios.c vgasrc/vgafb.c \ - vgasrc/vgatables.c vgasrc/vgafonts.c vgasrc/vbe.c \ - vgasrc/stdvga.c vgasrc/clext.c vgasrc/bochsvga.c vgasrc/geodevga.c +SRCVGA=src/output.c src/util.c src/pci.c \ + vgasrc/vgabios.c vgasrc/vgafb.c vgasrc/vgafonts.c vgasrc/vbe.c \ + vgasrc/vgatables.c vgasrc/stdvga.c vgasrc/stdvgaio.c \ + vgasrc/clext.c vgasrc/bochsvga.c vgasrc/geodevga.c
CFLAGS16VGA = $(CFLAGS16INC) -g -Isrc
diff --git a/vgasrc/clext.c b/vgasrc/clext.c index 413add5..d6fa7a2 100644 --- a/vgasrc/clext.c +++ b/vgasrc/clext.c @@ -374,12 +374,12 @@ cirrus_switch_mode(struct cirrus_mode_s *table) outb(0xff, VGAREG_PEL_MASK);
u8 memmodel = GET_GLOBAL(table->info.memmodel); - u8 v = stdvga_get_single_palette_reg(0x10) & 0xfe; + u8 on = 0; if (memmodel == MM_PLANAR) - v |= 0x41; + on = 0x41; else if (memmodel != MM_TEXT) - v |= 0x01; - stdvga_set_single_palette_reg(0x10, v); + on = 0x01; + stdvga_attr_mask(0x10, 0x01, on); }
static u8 diff --git a/vgasrc/stdvga.c b/vgasrc/stdvga.c index 6998cd0..0345a81 100644 --- a/vgasrc/stdvga.c +++ b/vgasrc/stdvga.c @@ -1,4 +1,4 @@ -// VGA io port access +// Standard VGA driver code // // Copyright (C) 2009 Kevin O'Connor kevin@koconnor.net // Copyright (C) 2001-2008 the LGPL VGABios developers Team @@ -95,26 +95,6 @@ stdvga_set_palette(u8 palid) }
void -stdvga_set_single_palette_reg(u8 reg, u8 val) -{ - inb(VGAREG_ACTL_RESET); - outb(reg, VGAREG_ACTL_ADDRESS); - outb(val, VGAREG_ACTL_WRITE_DATA); - outb(0x20, VGAREG_ACTL_ADDRESS); -} - -u8 -stdvga_get_single_palette_reg(u8 reg) -{ - inb(VGAREG_ACTL_RESET); - outb(reg, VGAREG_ACTL_ADDRESS); - u8 v = inb(VGAREG_ACTL_READ_DATA); - inb(VGAREG_ACTL_RESET); - outb(0x20, VGAREG_ACTL_ADDRESS); - return v; -} - -void stdvga_set_all_palette_reg(u16 seg, u8 *data_far) { inb(VGAREG_ACTL_RESET); @@ -206,55 +186,13 @@ stdvga_read_video_dac_state(u8 *pmode, u8 *curpage) ****************************************************************/
void -stdvga_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count) -{ - outb(start, VGAREG_DAC_WRITE_ADDRESS); - while (count) { - outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); - data_far++; - outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); - data_far++; - outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); - data_far++; - count--; - } -} - -void -stdvga_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count) -{ - outb(start, VGAREG_DAC_READ_ADDRESS); - while (count) { - SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); - data_far++; - SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); - data_far++; - SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); - data_far++; - count--; - } -} - -void -stdvga_set_pel_mask(u8 val) -{ - outb(val, VGAREG_PEL_MASK); -} - -u8 -stdvga_get_pel_mask(void) -{ - return inb(VGAREG_PEL_MASK); -} - -void stdvga_save_dac_state(u16 seg, struct saveDACcolors *info) { /* XXX: check this */ SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE)); SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS)); SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK)); - stdvga_get_dac_regs(seg, info->dac, 0, 256); + stdvga_dac_read(seg, info->dac, 0, 256); SET_FARVAR(seg, info->color_select, 0); }
@@ -262,7 +200,7 @@ void stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info) { outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK); - stdvga_set_dac_regs(seg, info->dac, 0, 256); + stdvga_dac_write(seg, info->dac, 0, 256); outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS); }
@@ -273,14 +211,14 @@ stdvga_perform_gray_scale_summing(u16 start, u16 count) int i; for (i = start; i < start+count; i++) { u8 rgb[3]; - stdvga_get_dac_regs(GET_SEG(SS), rgb, i, 1); + stdvga_dac_read(GET_SEG(SS), rgb, i, 1);
// intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue ) u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8; if (intensity > 0x3f) intensity = 0x3f;
- stdvga_set_dac_regs(GET_SEG(SS), rgb, i, 1); + stdvga_dac_write(GET_SEG(SS), rgb, i, 1); } stdvga_screen_enable(); } @@ -291,18 +229,6 @@ stdvga_perform_gray_scale_summing(u16 start, u16 count) ****************************************************************/
void -stdvga_sequ_write(u8 index, u8 value) -{ - outw((value<<8) | index, VGAREG_SEQU_ADDRESS); -} - -void -stdvga_grdc_write(u8 index, u8 value) -{ - outw((value<<8) | index, VGAREG_GRDC_ADDRESS); -} - -void stdvga_set_text_block_specifier(u8 spec) { outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS); @@ -360,7 +286,7 @@ stdvga_load_font(u16 seg, void *src_far, u16 count u16 stdvga_get_crtc(void) { - if (inb(VGAREG_READ_MISC_OUTPUT) & 1) + if (stdvga_misc_read() & 1) return VGAREG_VGA_CRTC_ADDRESS; return VGAREG_MDA_CRTC_ADDRESS; } @@ -552,18 +478,18 @@ stdvga_set_mode(int mode, int flags)
// if palette loading (bit 3 of modeset ctl = 0) if (!(flags & MF_NOPALETTE)) { // Set the PEL mask - stdvga_set_pel_mask(GET_GLOBAL(stdmode_g->pelmask)); + stdvga_pelmask_write(GET_GLOBAL(stdmode_g->pelmask));
// From which palette u8 *palette_g = GET_GLOBAL(stdmode_g->dac); u16 palsize = GET_GLOBAL(stdmode_g->dacsize) / 3;
// Always 256*3 values - stdvga_set_dac_regs(get_global_seg(), palette_g, 0, palsize); + stdvga_dac_write(get_global_seg(), palette_g, 0, palsize); u16 i; for (i = palsize; i < 0x0100; i++) { static u8 rgb[3] VAR16; - stdvga_set_dac_regs(get_global_seg(), rgb, i, 1); + stdvga_dac_write(get_global_seg(), rgb, i, 1); }
if (flags & MF_GRAYSUM) diff --git a/vgasrc/stdvga.h b/vgasrc/stdvga.h index 033a711..abda606 100644 --- a/vgasrc/stdvga.h +++ b/vgasrc/stdvga.h @@ -85,27 +85,42 @@ struct saveDACcolors { // vgatables.c struct vgamode_s *stdvga_find_mode(int mode);
+// stdvgaio.c +u8 stdvga_pelmask_read(void); +void stdvga_pelmask_write(u8 val); +u8 stdvga_misc_read(void); +void stdvga_misc_write(u8 value); +void stdvga_misc_mask(u8 off, u8 on); +u8 stdvga_sequ_read(u8 index); +void stdvga_sequ_write(u8 index, u8 value); +void stdvga_sequ_mask(u8 index, u8 off, u8 on); +u8 stdvga_grdc_read(u8 index); +void stdvga_grdc_write(u8 index, u8 value); +void stdvga_grdc_mask(u8 index, u8 off, u8 on); +u8 stdvga_crtc_read(u16 crtc_addr, u8 index); +void stdvga_crtc_write(u16 crtc_addr, u8 index, u8 value); +void stdvga_crtc_mask(u16 crtc_addr, u8 index, u8 off, u8 on); +u8 stdvga_attr_read(u8 index); +void stdvga_attr_write(u8 index, u8 value); +void stdvga_attr_mask(u8 index, u8 off, u8 on); +u8 stdvga_attrindex_read(void); +void stdvga_attrindex_write(u8 value); +void stdvga_dac_read(u16 seg, u8 *data_far, u8 start, int count); +void stdvga_dac_write(u16 seg, u8 *data_far, u8 start, int count); + // stdvga.c void stdvga_set_border_color(u8 color); void stdvga_set_overscan_border_color(u8 color); u8 stdvga_get_overscan_border_color(void); void stdvga_set_palette(u8 palid); -void stdvga_set_single_palette_reg(u8 reg, u8 val); -u8 stdvga_get_single_palette_reg(u8 reg); void stdvga_set_all_palette_reg(u16 seg, u8 *data_far); void stdvga_get_all_palette_reg(u16 seg, u8 *data_far); void stdvga_toggle_intensity(u8 flag); void stdvga_select_video_dac_color_page(u8 flag, u8 data); void stdvga_read_video_dac_state(u8 *pmode, u8 *curpage); -void stdvga_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count); -void stdvga_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count); -void stdvga_set_pel_mask(u8 val); -u8 stdvga_get_pel_mask(void); void stdvga_save_dac_state(u16 seg, struct saveDACcolors *info); void stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info); void stdvga_perform_gray_scale_summing(u16 start, u16 count); -void stdvga_sequ_write(u8 index, u8 value); -void stdvga_grdc_write(u8 index, u8 value); void stdvga_set_text_block_specifier(u8 spec); void stdvga_load_font(u16 seg, void *src_far, u16 count , u16 start, u8 destflags, u8 fontsize); diff --git a/vgasrc/stdvgaio.c b/vgasrc/stdvgaio.c new file mode 100644 index 0000000..9cec179 --- /dev/null +++ b/vgasrc/stdvgaio.c @@ -0,0 +1,185 @@ +// Standard VGA IO port access +// +// Copyright (C) 2012 Kevin O'Connor kevin@koconnor.net +// +// This file may be distributed under the terms of the GNU LGPLv3 license. + +#include "stdvga.h" // stdvga_pelmask_read +#include "ioport.h" // inb + +u8 +stdvga_pelmask_read(void) +{ + return inb(VGAREG_PEL_MASK); +} + +void +stdvga_pelmask_write(u8 value) +{ + outb(value, VGAREG_PEL_MASK); +} + + +u8 +stdvga_misc_read(void) +{ + return inb(VGAREG_READ_MISC_OUTPUT); +} + +void +stdvga_misc_write(u8 value) +{ + outb(value, VGAREG_WRITE_MISC_OUTPUT); +} + +void +stdvga_misc_mask(u8 off, u8 on) +{ + stdvga_misc_write((stdvga_misc_read() & ~off) | on); +} + + +u8 +stdvga_sequ_read(u8 index) +{ + outb(index, VGAREG_SEQU_ADDRESS); + return inb(VGAREG_SEQU_DATA); +} + +void +stdvga_sequ_write(u8 index, u8 value) +{ + outw((value<<8) | index, VGAREG_SEQU_ADDRESS); +} + +void +stdvga_sequ_mask(u8 index, u8 off, u8 on) +{ + outb(index, VGAREG_SEQU_ADDRESS); + u8 v = inb(VGAREG_SEQU_DATA); + outb((v & ~off) | on, VGAREG_SEQU_DATA); +} + + +u8 +stdvga_grdc_read(u8 index) +{ + outb(index, VGAREG_GRDC_ADDRESS); + return inb(VGAREG_GRDC_DATA); +} + +void +stdvga_grdc_write(u8 index, u8 value) +{ + outw((value<<8) | index, VGAREG_GRDC_ADDRESS); +} + +void +stdvga_grdc_mask(u8 index, u8 off, u8 on) +{ + outb(index, VGAREG_GRDC_ADDRESS); + u8 v = inb(VGAREG_GRDC_DATA); + outb((v & ~off) | on, VGAREG_GRDC_DATA); +} + + +u8 +stdvga_crtc_read(u16 crtc_addr, u8 index) +{ + outb(index, crtc_addr); + return inb(crtc_addr + 1); +} + +void +stdvga_crtc_write(u16 crtc_addr, u8 index, u8 value) +{ + outb(index, crtc_addr); + outb(value, crtc_addr + 1); +} + +void +stdvga_crtc_mask(u16 crtc_addr, u8 index, u8 off, u8 on) +{ + outb(index, crtc_addr); + u8 v = inb(crtc_addr + 1); + outb((v & ~off) | on, crtc_addr + 1); +} + + +u8 +stdvga_attr_read(u8 index) +{ + inb(VGAREG_ACTL_RESET); + u8 orig = inb(VGAREG_ACTL_ADDRESS); + outb(index, VGAREG_ACTL_ADDRESS); + u8 v = inb(VGAREG_ACTL_READ_DATA); + inb(VGAREG_ACTL_RESET); + outb(orig, VGAREG_ACTL_ADDRESS); + return v; +} + +void +stdvga_attr_write(u8 index, u8 value) +{ + inb(VGAREG_ACTL_RESET); + u8 orig = inb(VGAREG_ACTL_ADDRESS); + outb(index, VGAREG_ACTL_ADDRESS); + outb(value, VGAREG_ACTL_WRITE_DATA); + outb(orig, VGAREG_ACTL_ADDRESS); +} + +void +stdvga_attr_mask(u8 index, u8 off, u8 on) +{ + inb(VGAREG_ACTL_RESET); + u8 orig = inb(VGAREG_ACTL_ADDRESS); + outb(index, VGAREG_ACTL_ADDRESS); + u8 v = inb(VGAREG_ACTL_READ_DATA); + outb((v & ~off) | on, VGAREG_ACTL_WRITE_DATA); + outb(orig, VGAREG_ACTL_ADDRESS); +} + +u8 +stdvga_attrindex_read(void) +{ + inb(VGAREG_ACTL_RESET); + return inb(VGAREG_ACTL_ADDRESS); +} + +void +stdvga_attrindex_write(u8 value) +{ + inb(VGAREG_ACTL_RESET); + outb(value, VGAREG_ACTL_ADDRESS); +} + + +void +stdvga_dac_read(u16 seg, u8 *data_far, u8 start, int count) +{ + outb(start, VGAREG_DAC_READ_ADDRESS); + while (count) { + SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); + data_far++; + SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); + data_far++; + SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); + data_far++; + count--; + } +} + +void +stdvga_dac_write(u16 seg, u8 *data_far, u8 start, int count) +{ + outb(start, VGAREG_DAC_WRITE_ADDRESS); + while (count) { + outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); + data_far++; + outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); + data_far++; + outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); + data_far++; + count--; + } +} diff --git a/vgasrc/vgabios.c b/vgasrc/vgabios.c index 8ab5baa..84b112c 100644 --- a/vgasrc/vgabios.c +++ b/vgasrc/vgabios.c @@ -575,7 +575,7 @@ handle_101000(struct bregs *regs) { if (regs->bl > 0x14) return; - stdvga_set_single_palette_reg(regs->bl, regs->bh); + stdvga_attr_write(regs->bl, regs->bh); }
static void @@ -601,7 +601,7 @@ handle_101007(struct bregs *regs) { if (regs->bl > 0x14) return; - regs->bh = stdvga_get_single_palette_reg(regs->bl); + regs->bh = stdvga_attr_read(regs->bl); }
static void @@ -620,13 +620,13 @@ static void noinline handle_101010(struct bregs *regs) { u8 rgb[3] = {regs->dh, regs->ch, regs->cl}; - stdvga_set_dac_regs(GET_SEG(SS), rgb, regs->bx, 1); + stdvga_dac_write(GET_SEG(SS), rgb, regs->bx, 1); }
static void handle_101012(struct bregs *regs) { - stdvga_set_dac_regs(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx); + stdvga_dac_write(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx); }
static void @@ -639,7 +639,7 @@ static void noinline handle_101015(struct bregs *regs) { u8 rgb[3]; - stdvga_get_dac_regs(GET_SEG(SS), rgb, regs->bx, 1); + stdvga_dac_read(GET_SEG(SS), rgb, regs->bx, 1); regs->dh = rgb[0]; regs->ch = rgb[1]; regs->cl = rgb[2]; @@ -648,19 +648,19 @@ handle_101015(struct bregs *regs) static void handle_101017(struct bregs *regs) { - stdvga_get_dac_regs(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx); + stdvga_dac_read(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx); }
static void handle_101018(struct bregs *regs) { - stdvga_set_pel_mask(regs->bl); + stdvga_pelmask_write(regs->bl); }
static void handle_101019(struct bregs *regs) { - regs->bl = stdvga_get_pel_mask(); + regs->bl = stdvga_pelmask_read(); }
static void
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- vgasrc/stdvga.c | 316 ++++++++++++++++--------------------------------------- 1 files changed, 90 insertions(+), 226 deletions(-)
diff --git a/vgasrc/stdvga.c b/vgasrc/stdvga.c index 0345a81..d1841bf 100644 --- a/vgasrc/stdvga.c +++ b/vgasrc/stdvga.c @@ -12,102 +12,53 @@ #include "util.h" // memcpy_far #include "vbe.h" // VBE_RETURN_STATUS_FAILED
-// TODO -// * replace direct in/out calls with wrapper functions -
/**************************************************************** * Attribute control ****************************************************************/
-static void -stdvga_screen_disable(void) -{ - inb(VGAREG_ACTL_RESET); - outb(0x00, VGAREG_ACTL_ADDRESS); -} - -static void -stdvga_screen_enable(void) -{ - inb(VGAREG_ACTL_RESET); - outb(0x20, VGAREG_ACTL_ADDRESS); -} - void stdvga_set_border_color(u8 color) { - inb(VGAREG_ACTL_RESET); - outb(0x00, VGAREG_ACTL_ADDRESS); u8 v1 = color & 0x0f; if (v1 & 0x08) v1 += 0x08; - outb(v1, VGAREG_ACTL_WRITE_DATA); + stdvga_attr_write(0x00, v1);
- u8 v2 = color & 0x10; int i; - for (i = 1; i < 4; i++) { - outb(i, VGAREG_ACTL_ADDRESS); - - u8 cur = inb(VGAREG_ACTL_READ_DATA); - cur &= 0xef; - cur |= v2; - outb(cur, VGAREG_ACTL_WRITE_DATA); - } - outb(0x20, VGAREG_ACTL_ADDRESS); + for (i = 1; i < 4; i++) + stdvga_attr_mask(i, 0x10, color & 0x10); }
void stdvga_set_overscan_border_color(u8 color) { - inb(VGAREG_ACTL_RESET); - outb(0x11, VGAREG_ACTL_ADDRESS); - outb(color, VGAREG_ACTL_WRITE_DATA); - outb(0x20, VGAREG_ACTL_ADDRESS); + stdvga_attr_write(0x11, color); }
u8 stdvga_get_overscan_border_color(void) { - inb(VGAREG_ACTL_RESET); - outb(0x11, VGAREG_ACTL_ADDRESS); - u8 v = inb(VGAREG_ACTL_READ_DATA); - inb(VGAREG_ACTL_RESET); - outb(0x20, VGAREG_ACTL_ADDRESS); - return v; + return stdvga_attr_read(0x11); }
void stdvga_set_palette(u8 palid) { - inb(VGAREG_ACTL_RESET); - palid &= 0x01; int i; - for (i = 1; i < 4; i++) { - outb(i, VGAREG_ACTL_ADDRESS); - - u8 v = inb(VGAREG_ACTL_READ_DATA); - v &= 0xfe; - v |= palid; - outb(v, VGAREG_ACTL_WRITE_DATA); - } - outb(0x20, VGAREG_ACTL_ADDRESS); + for (i = 1; i < 4; i++) + stdvga_attr_mask(i, 0x01, palid & 0x01); }
void stdvga_set_all_palette_reg(u16 seg, u8 *data_far) { - inb(VGAREG_ACTL_RESET); int i; for (i = 0; i < 0x10; i++) { - outb(i, VGAREG_ACTL_ADDRESS); - u8 val = GET_FARVAR(seg, *data_far); - outb(val, VGAREG_ACTL_WRITE_DATA); + stdvga_attr_write(i, GET_FARVAR(seg, *data_far)); data_far++; } - outb(0x11, VGAREG_ACTL_ADDRESS); - outb(GET_FARVAR(seg, *data_far), VGAREG_ACTL_WRITE_DATA); - outb(0x20, VGAREG_ACTL_ADDRESS); + stdvga_attr_write(0x11, GET_FARVAR(seg, *data_far)); }
void @@ -115,67 +66,41 @@ stdvga_get_all_palette_reg(u16 seg, u8 *data_far) { int i; for (i = 0; i < 0x10; i++) { - inb(VGAREG_ACTL_RESET); - outb(i, VGAREG_ACTL_ADDRESS); - SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA)); + SET_FARVAR(seg, *data_far, stdvga_attr_read(i)); data_far++; } - inb(VGAREG_ACTL_RESET); - outb(0x11, VGAREG_ACTL_ADDRESS); - SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA)); - inb(VGAREG_ACTL_RESET); - outb(0x20, VGAREG_ACTL_ADDRESS); + SET_FARVAR(seg, *data_far, stdvga_attr_read(0x11)); }
void stdvga_toggle_intensity(u8 flag) { - inb(VGAREG_ACTL_RESET); - outb(0x10, VGAREG_ACTL_ADDRESS); - u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0xf7) | ((flag & 0x01) << 3); - outb(val, VGAREG_ACTL_WRITE_DATA); - outb(0x20, VGAREG_ACTL_ADDRESS); + stdvga_attr_mask(0x10, 0x08, (flag & 0x01) << 3); }
void stdvga_select_video_dac_color_page(u8 flag, u8 data) { - inb(VGAREG_ACTL_RESET); - outb(0x10, VGAREG_ACTL_ADDRESS); - u8 val = inb(VGAREG_ACTL_READ_DATA); if (!(flag & 0x01)) { // select paging mode - val = (val & 0x7f) | (data << 7); - outb(val, VGAREG_ACTL_WRITE_DATA); - outb(0x20, VGAREG_ACTL_ADDRESS); + stdvga_attr_mask(0x10, 0x80, data << 7); return; } // select page - inb(VGAREG_ACTL_RESET); - outb(0x14, VGAREG_ACTL_ADDRESS); + u8 val = stdvga_attr_read(0x10); if (!(val & 0x80)) data <<= 2; data &= 0x0f; - outb(data, VGAREG_ACTL_WRITE_DATA); - outb(0x20, VGAREG_ACTL_ADDRESS); + stdvga_attr_write(0x14, data); }
void stdvga_read_video_dac_state(u8 *pmode, u8 *curpage) { - inb(VGAREG_ACTL_RESET); - outb(0x10, VGAREG_ACTL_ADDRESS); - u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7; - - inb(VGAREG_ACTL_RESET); - outb(0x14, VGAREG_ACTL_ADDRESS); - u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f; + u8 val1 = stdvga_attr_read(0x10) >> 7; + u8 val2 = stdvga_attr_read(0x14) & 0x0f; if (!(val1 & 0x01)) val2 >>= 2; - - inb(VGAREG_ACTL_RESET); - outb(0x20, VGAREG_ACTL_ADDRESS); - *pmode = val1; *curpage = val2; } @@ -191,7 +116,7 @@ stdvga_save_dac_state(u16 seg, struct saveDACcolors *info) /* XXX: check this */ SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE)); SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS)); - SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK)); + SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read()); stdvga_dac_read(seg, info->dac, 0, 256); SET_FARVAR(seg, info->color_select, 0); } @@ -199,7 +124,7 @@ stdvga_save_dac_state(u16 seg, struct saveDACcolors *info) void stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info) { - outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK); + stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask)); stdvga_dac_write(seg, info->dac, 0, 256); outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS); } @@ -207,7 +132,7 @@ stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info) void stdvga_perform_gray_scale_summing(u16 start, u16 count) { - stdvga_screen_disable(); + stdvga_attrindex_write(0x00); int i; for (i = start; i < start+count; i++) { u8 rgb[3]; @@ -220,7 +145,7 @@ stdvga_perform_gray_scale_summing(u16 start, u16 count)
stdvga_dac_write(GET_SEG(SS), rgb, i, 1); } - stdvga_screen_enable(); + stdvga_attrindex_write(0x20); }
@@ -231,7 +156,7 @@ stdvga_perform_gray_scale_summing(u16 start, u16 count) void stdvga_set_text_block_specifier(u8 spec) { - outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS); + stdvga_sequ_write(0x03, spec); }
@@ -242,26 +167,26 @@ stdvga_set_text_block_specifier(u8 spec) static void get_font_access(void) { - outw(0x0100, VGAREG_SEQU_ADDRESS); - outw(0x0402, VGAREG_SEQU_ADDRESS); - outw(0x0704, VGAREG_SEQU_ADDRESS); - outw(0x0300, VGAREG_SEQU_ADDRESS); - outw(0x0204, VGAREG_GRDC_ADDRESS); - outw(0x0005, VGAREG_GRDC_ADDRESS); - outw(0x0406, VGAREG_GRDC_ADDRESS); + stdvga_sequ_write(0x00, 0x01); + stdvga_sequ_write(0x02, 0x04); + stdvga_sequ_write(0x04, 0x07); + stdvga_sequ_write(0x00, 0x03); + stdvga_grdc_write(0x04, 0x02); + stdvga_grdc_write(0x05, 0x00); + stdvga_grdc_write(0x06, 0x04); }
static void release_font_access(void) { - outw(0x0100, VGAREG_SEQU_ADDRESS); - outw(0x0302, VGAREG_SEQU_ADDRESS); - outw(0x0304, VGAREG_SEQU_ADDRESS); - outw(0x0300, VGAREG_SEQU_ADDRESS); - u16 v = (inb(VGAREG_READ_MISC_OUTPUT) & 0x01) ? 0x0e : 0x0a; - outw((v << 8) | 0x06, VGAREG_GRDC_ADDRESS); - outw(0x0004, VGAREG_GRDC_ADDRESS); - outw(0x1005, VGAREG_GRDC_ADDRESS); + stdvga_sequ_write(0x00, 0x01); + stdvga_sequ_write(0x02, 0x03); + stdvga_sequ_write(0x04, 0x03); + stdvga_sequ_write(0x00, 0x03); + u16 v = (stdvga_misc_read() & 0x01) ? 0x0e : 0x0a; + stdvga_grdc_write(0x06, v); + stdvga_grdc_write(0x04, 0x00); + stdvga_grdc_write(0x05, 0x10); }
void @@ -295,40 +220,30 @@ void stdvga_set_cursor_shape(u8 start, u8 end) { u16 crtc_addr = stdvga_get_crtc(); - outb(0x0a, crtc_addr); - outb(start, crtc_addr + 1); - outb(0x0b, crtc_addr); - outb(end, crtc_addr + 1); + stdvga_crtc_write(crtc_addr, 0x0a, start); + stdvga_crtc_write(crtc_addr, 0x0b, end); }
void stdvga_set_active_page(u16 address) { u16 crtc_addr = stdvga_get_crtc(); - outb(0x0c, crtc_addr); - outb((address & 0xff00) >> 8, crtc_addr + 1); - outb(0x0d, crtc_addr); - outb(address & 0x00ff, crtc_addr + 1); + stdvga_crtc_write(crtc_addr, 0x0c, address >> 8); + stdvga_crtc_write(crtc_addr, 0x0d, address); }
void stdvga_set_cursor_pos(u16 address) { u16 crtc_addr = stdvga_get_crtc(); - outb(0x0e, crtc_addr); - outb((address & 0xff00) >> 8, crtc_addr + 1); - outb(0x0f, crtc_addr); - outb(address & 0x00ff, crtc_addr + 1); + stdvga_crtc_write(crtc_addr, 0x0e, address >> 8); + stdvga_crtc_write(crtc_addr, 0x0f, address); }
void stdvga_set_scan_lines(u8 lines) { - u16 crtc_addr = stdvga_get_crtc(); - outb(0x09, crtc_addr); - u8 crtc_r9 = inb(crtc_addr + 1); - crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1); - outb(crtc_r9, crtc_addr + 1); + stdvga_crtc_mask(stdvga_get_crtc(), 0x09, 0x1f, lines - 1); }
// Get vertical display end @@ -336,10 +251,8 @@ u16 stdvga_get_vde(void) { u16 crtc_addr = stdvga_get_crtc(); - outb(0x12, crtc_addr); - u16 vde = inb(crtc_addr + 1); - outb(0x07, crtc_addr); - u8 ovl = inb(crtc_addr + 1); + u16 vde = stdvga_crtc_read(crtc_addr, 0x12); + u8 ovl = stdvga_crtc_read(crtc_addr, 0x07); vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1); return vde; } @@ -356,35 +269,22 @@ stdvga_save_state(u16 seg, struct saveVideoHardware *info) SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS)); SET_FARVAR(seg, info->crtc_index, inb(crtc_addr)); SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS)); - inb(VGAREG_ACTL_RESET); - u16 ar_index = inb(VGAREG_ACTL_ADDRESS); - SET_FARVAR(seg, info->actl_index, ar_index); + SET_FARVAR(seg, info->actl_index, stdvga_attrindex_read()); SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
- u16 i; - for (i=0; i<4; i++) { - outb(i+1, VGAREG_SEQU_ADDRESS); - SET_FARVAR(seg, info->sequ_regs[i], inb(VGAREG_SEQU_DATA)); - } - outb(0, VGAREG_SEQU_ADDRESS); - SET_FARVAR(seg, info->sequ0, inb(VGAREG_SEQU_DATA)); + int i; + for (i=0; i<4; i++) + SET_FARVAR(seg, info->sequ_regs[i], stdvga_sequ_read(i+1)); + SET_FARVAR(seg, info->sequ0, stdvga_sequ_read(0));
- for (i=0; i<25; i++) { - outb(i, crtc_addr); - SET_FARVAR(seg, info->crtc_regs[i], inb(crtc_addr + 1)); - } + for (i=0; i<25; i++) + SET_FARVAR(seg, info->crtc_regs[i], stdvga_crtc_read(crtc_addr, i));
- for (i=0; i<20; i++) { - inb(VGAREG_ACTL_RESET); - outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS); - SET_FARVAR(seg, info->actl_regs[i], inb(VGAREG_ACTL_READ_DATA)); - } - inb(VGAREG_ACTL_RESET); + for (i=0; i<20; i++) + SET_FARVAR(seg, info->actl_regs[i], stdvga_attr_read(i));
- for (i=0; i<9; i++) { - outb(i, VGAREG_GRDC_ADDRESS); - SET_FARVAR(seg, info->grdc_regs[i], inb(VGAREG_GRDC_DATA)); - } + for (i=0; i<9; i++) + SET_FARVAR(seg, info->grdc_regs[i], stdvga_grdc_read(i));
SET_FARVAR(seg, info->crtc_addr, crtc_addr);
@@ -396,51 +296,31 @@ stdvga_save_state(u16 seg, struct saveVideoHardware *info) void stdvga_restore_state(u16 seg, struct saveVideoHardware *info) { - // Reset Attribute Ctl flip-flop - inb(VGAREG_ACTL_RESET); - - u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr); - - u16 i; - for (i=0; i<4; i++) { - outb(i+1, VGAREG_SEQU_ADDRESS); - outb(GET_FARVAR(seg, info->sequ_regs[i]), VGAREG_SEQU_DATA); - } - outb(0, VGAREG_SEQU_ADDRESS); - outb(GET_FARVAR(seg, info->sequ0), VGAREG_SEQU_DATA); + int i; + for (i=0; i<4; i++) + stdvga_sequ_write(i+1, GET_FARVAR(seg, info->sequ_regs[i])); + stdvga_sequ_write(0x00, GET_FARVAR(seg, info->sequ0));
// Disable CRTC write protection - outw(0x0011, crtc_addr); + u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr); + stdvga_crtc_write(crtc_addr, 0x11, 0x00); // Set CRTC regs for (i=0; i<25; i++) - if (i != 0x11) { - outb(i, crtc_addr); - outb(GET_FARVAR(seg, info->crtc_regs[i]), crtc_addr + 1); - } + if (i != 0x11) + stdvga_crtc_write(crtc_addr, i, GET_FARVAR(seg, info->crtc_regs[i])); // select crtc base address - u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01; - if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS) - v |= 0x01; - outb(v, VGAREG_WRITE_MISC_OUTPUT); + stdvga_misc_mask(0x01, crtc_addr == VGAREG_VGA_CRTC_ADDRESS ? 0x01 : 0x00);
// enable write protection if needed - outb(0x11, crtc_addr); - outb(GET_FARVAR(seg, info->crtc_regs[0x11]), crtc_addr + 1); + stdvga_crtc_write(crtc_addr, 0x11, GET_FARVAR(seg, info->crtc_regs[0x11]));
// Set Attribute Ctl - u16 ar_index = GET_FARVAR(seg, info->actl_index); - inb(VGAREG_ACTL_RESET); - for (i=0; i<20; i++) { - outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS); - outb(GET_FARVAR(seg, info->actl_regs[i]), VGAREG_ACTL_WRITE_DATA); - } - outb(ar_index, VGAREG_ACTL_ADDRESS); - inb(VGAREG_ACTL_RESET); + for (i=0; i<20; i++) + stdvga_attr_write(i, GET_FARVAR(seg, info->actl_regs[i])); + stdvga_attrindex_write(GET_FARVAR(seg, info->actl_index));
- for (i=0; i<9; i++) { - outb(i, VGAREG_GRDC_ADDRESS); - outb(GET_FARVAR(seg, info->grdc_regs[i]), VGAREG_GRDC_DATA); - } + for (i=0; i<9; i++) + stdvga_grdc_write(i, GET_FARVAR(seg, info->grdc_regs[i]));
outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS); outb(GET_FARVAR(seg, info->crtc_index), crtc_addr); @@ -486,7 +366,7 @@ stdvga_set_mode(int mode, int flags)
// Always 256*3 values stdvga_dac_write(get_global_seg(), palette_g, 0, palsize); - u16 i; + int i; for (i = palsize; i < 0x0100; i++) { static u8 rgb[3] VAR16; stdvga_dac_write(get_global_seg(), rgb, i, 1); @@ -496,34 +376,23 @@ stdvga_set_mode(int mode, int flags) stdvga_perform_gray_scale_summing(0x00, 0x100); }
- // Reset Attribute Ctl flip-flop - inb(VGAREG_ACTL_RESET); - // Set Attribute Ctl u8 *regs = GET_GLOBAL(stdmode_g->actl_regs); - u16 i; - for (i = 0; i <= 0x13; i++) { - outb(i, VGAREG_ACTL_ADDRESS); - outb(GET_GLOBAL(regs[i]), VGAREG_ACTL_WRITE_DATA); - } - outb(0x14, VGAREG_ACTL_ADDRESS); - outb(0x00, VGAREG_ACTL_WRITE_DATA); + int i; + for (i = 0; i <= 0x13; i++) + stdvga_attr_write(i, GET_GLOBAL(regs[i])); + stdvga_attr_write(0x14, 0x00);
// Set Sequencer Ctl - outb(0, VGAREG_SEQU_ADDRESS); - outb(0x03, VGAREG_SEQU_DATA); + stdvga_sequ_write(0x00, 0x03); regs = GET_GLOBAL(stdmode_g->sequ_regs); - for (i = 1; i <= 4; i++) { - outb(i, VGAREG_SEQU_ADDRESS); - outb(GET_GLOBAL(regs[i - 1]), VGAREG_SEQU_DATA); - } + for (i = 1; i <= 4; i++) + stdvga_sequ_write(i, GET_GLOBAL(regs[i - 1]));
// Set Grafx Ctl regs = GET_GLOBAL(stdmode_g->grdc_regs); - for (i = 0; i <= 8; i++) { - outb(i, VGAREG_GRDC_ADDRESS); - outb(GET_GLOBAL(regs[i]), VGAREG_GRDC_DATA); - } + for (i = 0; i <= 8; i++) + stdvga_grdc_write(i, GET_GLOBAL(regs[i]));
// Set CRTC address VGA or MDA u8 miscreg = GET_GLOBAL(stdmode_g->miscreg); @@ -532,20 +401,17 @@ stdvga_set_mode(int mode, int flags) crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
// Disable CRTC write protection - outw(0x0011, crtc_addr); + stdvga_crtc_write(crtc_addr, 0x11, 0x00); // Set CRTC regs regs = GET_GLOBAL(stdmode_g->crtc_regs); - for (i = 0; i <= 0x18; i++) { - outb(i, crtc_addr); - outb(GET_GLOBAL(regs[i]), crtc_addr + 1); - } + for (i = 0; i <= 0x18; i++) + stdvga_crtc_write(crtc_addr, i, GET_GLOBAL(regs[i]));
// Set the misc register - outb(miscreg, VGAREG_WRITE_MISC_OUTPUT); + stdvga_misc_write(miscreg);
// Enable video - outb(0x20, VGAREG_ACTL_ADDRESS); - inb(VGAREG_ACTL_RESET); + stdvga_attrindex_write(0x20);
// Clear screen if (!(flags & MF_NOCLEARMEM)) @@ -577,18 +443,16 @@ void stdvga_enable_video_addressing(u8 disable) { u8 v = (disable & 1) ? 0x00 : 0x02; - u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02; - outb(v | v2, VGAREG_WRITE_MISC_OUTPUT); + stdvga_misc_mask(0x02, v); }
int stdvga_init(void) { // switch to color mode and enable CPU access 480 lines - outb(0xc3, VGAREG_WRITE_MISC_OUTPUT); + stdvga_misc_write(0xc3); // more than 64k 3C4/04 - outb(0x04, VGAREG_SEQU_ADDRESS); - outb(0x02, VGAREG_SEQU_DATA); + stdvga_sequ_write(0x04, 0x02);
return 0; }
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- vgasrc/bochsvga.c | 53 +++++++++++++++++++---------------------------------- vgasrc/bochsvga.h | 2 +- 2 files changed, 20 insertions(+), 35 deletions(-)
diff --git a/vgasrc/bochsvga.c b/vgasrc/bochsvga.c index b7b1b05..07bf6cd 100644 --- a/vgasrc/bochsvga.c +++ b/vgasrc/bochsvga.c @@ -238,43 +238,28 @@ bochsvga_set_mode(int mode, int flags)
/* VGA compat setup */ //XXX: This probably needs some reverse engineering - u8 v; - outw(0x0011, VGAREG_VGA_CRTC_ADDRESS); - outw(((width * 4 - 1) << 8) | 0x1, VGAREG_VGA_CRTC_ADDRESS); + u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS; + stdvga_crtc_write(crtc_addr, 0x11, 0x00); + stdvga_crtc_write(crtc_addr, 0x01, width / 8 - 1); dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, width); - outw(((height - 1) << 8) | 0x12, VGAREG_VGA_CRTC_ADDRESS); - outw(((height - 1) & 0xff00) | 0x7, VGAREG_VGA_CRTC_ADDRESS); - v = inb(VGAREG_VGA_CRTC_DATA) & 0xbd; - if (v & 0x1) - v |= 0x2; - if (v & 0x2) + stdvga_crtc_write(crtc_addr, 0x12, height - 1); + u8 v = 0; + if ((height - 1) & 0x0100) + v |= 0x02; + if ((height - 1) & 0x0200) v |= 0x40; - outb(v, VGAREG_VGA_CRTC_DATA); - - outw(0x9, VGAREG_VGA_CRTC_ADDRESS); - outb(0x17, VGAREG_VGA_CRTC_ADDRESS); - outb(inb(VGAREG_VGA_CRTC_DATA) | 0x3, VGAREG_VGA_CRTC_DATA); - v = inb(VGAREG_ACTL_RESET); - outw(0x10, VGAREG_ACTL_ADDRESS); - v = inb(VGAREG_ACTL_READ_DATA) | 0x1; - outb(v, VGAREG_ACTL_ADDRESS); - outb(0x20, VGAREG_ACTL_ADDRESS); - outw(0x0506, VGAREG_GRDC_ADDRESS); - outw(0x0f02, VGAREG_SEQU_ADDRESS); + stdvga_crtc_mask(crtc_addr, 0x07, 0x00, v); + + stdvga_crtc_write(crtc_addr, 0x09, 0x00); + stdvga_crtc_mask(crtc_addr, 0x17, 0x00, 0x03); + stdvga_attr_mask(0x10, 0x00, 0x01); + stdvga_grdc_write(0x06, 0x05); + stdvga_sequ_write(0x02, 0x0f); if (depth >= 8) { - outb(0x14, VGAREG_VGA_CRTC_ADDRESS); - outb(inb(VGAREG_VGA_CRTC_DATA) | 0x40, VGAREG_VGA_CRTC_DATA); - v = inb(VGAREG_ACTL_RESET); - outw(0x10, VGAREG_ACTL_ADDRESS); - v = inb(VGAREG_ACTL_READ_DATA) | 0x40; - outb(v, VGAREG_ACTL_ADDRESS); - outb(0x20, VGAREG_ACTL_ADDRESS); - outb(0x04, VGAREG_SEQU_ADDRESS); - v = inb(VGAREG_SEQU_DATA) | 0x08; - outb(v, VGAREG_SEQU_DATA); - outb(0x05, VGAREG_GRDC_ADDRESS); - v = inb(VGAREG_GRDC_DATA) & 0x9f; - outb(v | 0x40, VGAREG_GRDC_DATA); + stdvga_crtc_mask(crtc_addr, 0x14, 0x00, 0x40); + stdvga_attr_mask(0x10, 0x00, 0x40); + stdvga_sequ_mask(0x04, 0x00, 0x08); + stdvga_grdc_mask(0x05, 0x20, 0x40); }
SET_BDA(vbe_mode, mode | flags); diff --git a/vgasrc/bochsvga.h b/vgasrc/bochsvga.h index a9cedbf..81fb8f7 100644 --- a/vgasrc/bochsvga.h +++ b/vgasrc/bochsvga.h @@ -2,7 +2,7 @@ #define __BOCHSVGA_H
#include "types.h" // u8 -#include "ioport.h" // outb +#include "ioport.h" // outw
#define VBE_DISPI_BANK_ADDRESS 0xA0000 #define VBE_DISPI_BANK_SIZE_KB 64
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- vgasrc/clext.c | 117 +++++++++++++++++++------------------------------------- 1 files changed, 39 insertions(+), 78 deletions(-)
diff --git a/vgasrc/clext.c b/vgasrc/clext.c index d6fa7a2..1de94c1 100644 --- a/vgasrc/clext.c +++ b/vgasrc/clext.c @@ -360,18 +360,18 @@ static void cirrus_switch_mode(struct cirrus_mode_s *table) { // Unlock cirrus special - outw(0x1206, VGAREG_SEQU_ADDRESS); + stdvga_sequ_write(0x06, 0x12); cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS); cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS); cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
- outb(0x00, VGAREG_PEL_MASK); - inb(VGAREG_PEL_MASK); - inb(VGAREG_PEL_MASK); - inb(VGAREG_PEL_MASK); - inb(VGAREG_PEL_MASK); - outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK); - outb(0xff, VGAREG_PEL_MASK); + stdvga_pelmask_write(0x00); + stdvga_pelmask_read(); + stdvga_pelmask_read(); + stdvga_pelmask_read(); + stdvga_pelmask_read(); + stdvga_pelmask_write(GET_GLOBAL(table->hidden_dac)); + stdvga_pelmask_write(0xff);
u8 memmodel = GET_GLOBAL(table->info.memmodel); u8 on = 0; @@ -386,25 +386,18 @@ static u8 cirrus_get_memsize(void) { // get DRAM band width - outb(0x0f, VGAREG_SEQU_ADDRESS); - u8 v = inb(VGAREG_SEQU_DATA); + u8 v = stdvga_sequ_read(0x0f); u8 x = (v >> 3) & 0x03; - if (x == 0x03) { - if (v & 0x80) - // 4MB - return 0x40; - // 2MB - return 0x20; - } + if (x == 0x03 && v & 0x80) + // 4MB + return 0x40; return 0x04 << x; }
static void cirrus_enable_16k_granularity(void) { - outb(0x0b, VGAREG_GRDC_ADDRESS); - u8 v = inb(VGAREG_GRDC_DATA); - outb(v | 0x20, VGAREG_GRDC_DATA); + stdvga_grdc_mask(0x0b, 0x00, 0x20); }
static void @@ -414,10 +407,10 @@ cirrus_clear_vram(u16 param) u8 count = cirrus_get_memsize() * 4; u8 i; for (i=0; i<count; i++) { - outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS); + stdvga_grdc_write(0x09, i); memset16_far(SEG_GRAPH, 0, param, 16 * 1024); } - outw(0x0009, VGAREG_GRDC_ADDRESS); + stdvga_grdc_write(0x09, 0x00); }
int @@ -444,8 +437,8 @@ clext_set_mode(int mode, int flags) static int cirrus_check(void) { - outw(0x9206, VGAREG_SEQU_ADDRESS); - return inb(VGAREG_SEQU_DATA) == 0x12; + stdvga_sequ_write(0x06, 0x92); + return stdvga_sequ_read(0x06) == 0x12; }
@@ -456,9 +449,7 @@ cirrus_check(void) static void clext_101280(struct bregs *regs) { - u16 crtc_addr = stdvga_get_crtc(); - outb(0x27, crtc_addr); - u8 v = inb(crtc_addr + 1); + u8 v = stdvga_crtc_read(stdvga_get_crtc(), 0x27); if (v == 0xa0) // 5430 regs->ax = 0x0032; @@ -481,9 +472,7 @@ clext_101281(struct bregs *regs) static void clext_101282(struct bregs *regs) { - u16 crtc_addr = stdvga_get_crtc(); - outb(0x27, crtc_addr); - regs->al = inb(crtc_addr + 1) & 0x03; + regs->al = stdvga_crtc_read(stdvga_get_crtc(), 0x27) & 0x03; regs->ah = 0xAF; }
@@ -577,8 +566,7 @@ clext_list_modes(u16 seg, u16 *dest, u16 *last) static u8 cirrus_get_bpp_bytes(void) { - outb(0x07, VGAREG_SEQU_ADDRESS); - u8 v = inb(VGAREG_SEQU_DATA) & 0x0e; + u8 v = stdvga_sequ_read(0x07) & 0x0e; if (v == 0x06) v &= 0x02; v >>= 1; @@ -592,23 +580,16 @@ cirrus_set_line_offset(u16 new_line_offset) { new_line_offset /= 8; u16 crtc_addr = stdvga_get_crtc(); - outb(0x13, crtc_addr); - outb(new_line_offset, crtc_addr + 1); - - outb(0x1b, crtc_addr); - u8 v = inb(crtc_addr + 1); - outb(((new_line_offset & 0x100) >> 4) | (v & 0xef), crtc_addr + 1); + stdvga_crtc_write(crtc_addr, 0x13, new_line_offset); + stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (new_line_offset & 0x100) >> 4); }
static u16 cirrus_get_line_offset(void) { u16 crtc_addr = stdvga_get_crtc(); - outb(0x13, crtc_addr); - u8 reg13 = inb(crtc_addr + 1); - outb(0x1b, crtc_addr); - u8 reg1b = inb(crtc_addr + 1); - + u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13); + u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b); return (((reg1b & 0x10) << 4) + reg13) * 8; }
@@ -616,38 +597,21 @@ static void cirrus_set_start_addr(u32 addr) { u16 crtc_addr = stdvga_get_crtc(); - outb(0x0d, crtc_addr); - outb(addr, crtc_addr + 1); - - outb(0x0c, crtc_addr); - outb(addr>>8, crtc_addr + 1); - - outb(0x1d, crtc_addr); - u8 v = inb(crtc_addr + 1); - outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1); - - outb(0x1b, crtc_addr); - v = inb(crtc_addr + 1); - outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2) - , crtc_addr + 1); + stdvga_crtc_write(crtc_addr, 0x0d, addr); + stdvga_crtc_write(crtc_addr, 0x0c, addr >> 8); + stdvga_crtc_mask(crtc_addr, 0x1d, 0x80, (addr & 0x0800) >> 4); + stdvga_crtc_mask(crtc_addr, 0x1b, 0x0d + , ((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7)); }
static u32 cirrus_get_start_addr(void) { u16 crtc_addr = stdvga_get_crtc(); - outb(0x0c, crtc_addr); - u8 b2 = inb(crtc_addr + 1); - - outb(0x0d, crtc_addr); - u8 b1 = inb(crtc_addr + 1); - - outb(0x1b, crtc_addr); - u8 b3 = inb(crtc_addr + 1); - - outb(0x1d, crtc_addr); - u8 b4 = inb(crtc_addr + 1); - + u8 b2 = stdvga_crtc_read(crtc_addr, 0x0c); + u8 b1 = stdvga_crtc_read(crtc_addr, 0x0d); + u8 b3 = stdvga_crtc_read(crtc_addr, 0x1b); + u8 b4 = stdvga_crtc_read(crtc_addr, 0x1d); return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15) | ((b4 & 0x80) << 12)); } @@ -661,11 +625,10 @@ cirrus_vesa_05h(struct bregs *regs) // set mempage if (regs->dx >= 0x100) goto fail; - outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS); + stdvga_grdc_write(regs->bl + 9, regs->dx); } else if (regs->bh == 1) { // get mempage - outb(regs->bl + 9, VGAREG_GRDC_ADDRESS); - regs->dx = inb(VGAREG_GRDC_DATA); + regs->dx = stdvga_grdc_read(regs->bl + 9); } else goto fail;
@@ -784,14 +747,12 @@ clext_init(void) SET_VGA(VBE_win_granularity, 16);
// memory setup - outb(0x0f, VGAREG_SEQU_ADDRESS); - u8 v = inb(VGAREG_SEQU_DATA); - outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS); + stdvga_sequ_mask(0x0f, 0xe7, 0x0a); // set vga mode - outw(0x0007, VGAREG_SEQU_ADDRESS); + stdvga_sequ_write(0x07, 0x00); // reset bitblt - outw(0x0431, VGAREG_GRDC_ADDRESS); - outw(0x0031, VGAREG_GRDC_ADDRESS); + stdvga_grdc_write(0x31, 0x04); + stdvga_grdc_write(0x31, 0x00);
return 0; }
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- vgasrc/geodevga.c | 19 +++++++------------ 1 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/vgasrc/geodevga.c b/vgasrc/geodevga.c index c1e4244..3da1b7c 100644 --- a/vgasrc/geodevga.c +++ b/vgasrc/geodevga.c @@ -12,7 +12,7 @@ #include "biosvar.h" // GET_BDA #include "vgabios.h" // VGAREG_* #include "util.h" // memset -#include "stdvga.h" // VGAREG_VGA_CRTC_ADDRESS +#include "stdvga.h" // stdvga_crtc_write
/**************************************************************** @@ -110,33 +110,28 @@ static int legacyio_check(void) ****************************************************************/ static void crtce_lock(void) { - outb(EXTENDED_REGISTER_LOCK , VGAREG_VGA_CRTC_ADDRESS); - outb(CRTCE_LOCK, VGAREG_VGA_CRTC_DATA); + stdvga_crtc_write(VGAREG_VGA_CRTC_ADDRESS, EXTENDED_REGISTER_LOCK + , CRTCE_LOCK); }
static void crtce_unlock(void) { - outb(EXTENDED_REGISTER_LOCK , VGAREG_VGA_CRTC_ADDRESS); - outb(CRTCE_UNLOCK, VGAREG_VGA_CRTC_DATA); + stdvga_crtc_write(VGAREG_VGA_CRTC_ADDRESS, EXTENDED_REGISTER_LOCK + , CRTCE_UNLOCK); }
static u8 crtce_read(u8 reg) { - u8 val; - crtce_unlock(); - outb(reg , VGAREG_VGA_CRTC_ADDRESS); - val = inb(VGAREG_VGA_CRTC_DATA); + u8 val = stdvga_crtc_read(VGAREG_VGA_CRTC_ADDRESS, reg); crtce_lock(); - return val; }
static void crtce_write(u8 reg, u8 val) { crtce_unlock(); - outb(reg , VGAREG_VGA_CRTC_ADDRESS); - outb(val, VGAREG_VGA_CRTC_DATA); + stdvga_crtc_write(VGAREG_VGA_CRTC_ADDRESS, reg, val); crtce_lock(); }
-
Kevin O'Connor