On Tue, Dec 24, 2013 at 02:09:17AM +0100, Idwer Vollering wrote:
2013/12/24 Kevin O'Connor kevin@koconnor.net:
On Sun, Dec 22, 2013 at 09:54:02PM -0500, Kevin O'Connor wrote: FYI, it seems my USB3 controller really wants to see 64bit writes to pci registers. With the change below (on top of the other changes) I can now boot my e350m1 from a USB3 flash drive.
I'm still seeing failures on my keyboard/mouse though:
[...]
This is captured on my f2a85-m, with CONFIG_DEBUG_LEVEL=7:
Hi Idwer,
From IRC, I understand that after you applied my last "status
direction" patch you were able to get your high speed flash device to work on the xhci controller, but not your keyboard.
Can you also try the patch below? I still can't get any high/low speed devices to work (though my super speed flash device does work). Maybe you'll have more luck with this patch though.
-Kevin
commit 5779c75cbea304d182a0291efd1f9422922200ce Author: Kevin O'Connor kevin@koconnor.net Date: Fri Dec 27 13:37:11 2013 -0500
xhci: Set the interval parameter on interrupt pipes.
Be sure to set the interval parameter when creating an interrupt based pipe.
Signed-off-by: Kevin O'Connor kevin@koconnor.net
diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index d0df6ee..9d5449c 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -895,6 +895,8 @@ xhci_alloc_pipe(struct usbdevice_s *usbdev in->slot.ctx[0] |= (31 << 27); // context entries
int e = pipe->epid-1; + if (eptype == USB_ENDPOINT_XFER_INT) + in->ep[e].ctx[0] = (usb_getFrameExp(usbdev, epdesc) + 3) << 16; in->ep[e].ctx[1] |= (eptype << 3); if (epdesc->bEndpointAddress & USB_DIR_IN) in->ep[e].ctx[1] |= (1 << 5);
2013/12/27 Kevin O'Connor kevin@koconnor.net:
On Tue, Dec 24, 2013 at 02:09:17AM +0100, Idwer Vollering wrote:
2013/12/24 Kevin O'Connor kevin@koconnor.net:
On Sun, Dec 22, 2013 at 09:54:02PM -0500, Kevin O'Connor wrote: FYI, it seems my USB3 controller really wants to see 64bit writes to pci registers. With the change below (on top of the other changes) I can now boot my e350m1 from a USB3 flash drive.
I'm still seeing failures on my keyboard/mouse though:
[...]
This is captured on my f2a85-m, with CONFIG_DEBUG_LEVEL=7:
Hi Idwer,
From IRC, I understand that after you applied my last "status direction" patch you were able to get your high speed flash device to work on the xhci controller, but not your keyboard.
Can you also try the patch below? I still can't get any high/low speed devices to work (though my super speed flash device does work). Maybe you'll have more luck with this patch though.
With an (low speed) USB keyboard in a non-XHCI port and an USB MSC in an XHCI port, and interrupting bootup with F12:
init usb xhci hcc=14042c3 hcs=4000820 XHCI init on dev 00:10.0: regs @ 0xf0148000, 4 ports, 32 slots XHCI extcap 0x1 @ f0148500 XHCI protocol USB 3.00, 2 ports (offset 1) XHCI protocol USB 2.00, 2 ports (offset 3) configure_xhci: resetting xhci_hub_detect port #1: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #2: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #3: 0x000202e1, powered, pls 7, speed 0 [ - ] xhci_hub_reset port #3: 0x000202e1, powered, pls 7, speed 0 [ - ] XHCI port #3: 0x00200e03, powered, enabled, pls 0, speed 3 [High] set_address 0x000edfe0 xhci_alloc_pipe: usbdev 0xbf102530, ring 0xbf11eb00, slotid 0, epid 1 xhci_cmd_enable_slot: xhci_trb_queue: ring 0xbf11ed00 [nidx 1, len 0] xhci_process_events: status change port #3 xhci_process_events: status change port #3 xhci_process_events: ring 0xbf11ed00 [trb 0xbf11ed00, evt 0xbf11ee00, type 33, eidx 1, cc 1] xhci_control: enable slot: got slotid 1 xhci_control: root port 3, route 0x0 xhci_cmd_address_device: slotid 1 xhci_trb_queue: ring 0xbf11ed00 [nidx 2, len 0] xhci_process_events: ring 0xbf11ed00 [trb 0xbf11ed10, evt 0xbf11ee00, type 33, eidx 2, cc 1] xhci_update_pipe: usbdev 0xbf102530, ring 0xbf11eb00, slotid 1, epid 1 config_usb: 0xbf11ec20 xhci_trb_queue: ring 0xbf11eb00 [nidx 1, len 8] xhci_trb_queue: ring 0xbf11eb00 [nidx 2, len 8] xhci_trb_queue: ring 0xbf11eb00 [nidx 3, len 0] xhci_xfer_kick: ring 0xbf11eb00, slotid 1, epid 1 xhci_process_events: ring 0xbf11eb00 [trb 0xbf11eb20, evt 0xbf11ec00, type 32, eidx 3, cc 1] device rev=0200 cls=00 sub=00 proto=00 size=40 xhci_update_pipe: usbdev 0xbf102530, ring 0xbf11eb00, slotid 1, epid 1 xhci_update_pipe: reconf ctl endpoint pkt size: 8 -> 64 xhci_cmd_evaluate_context: slotid 1, add 0x2, del 0x0 xhci_trb_queue: ring 0xbf11ed00 [nidx 3, len 0] xhci_process_events: ring 0xbf11ed00 [trb 0xbf11ed20, evt 0xbf11ee00, type 33, eidx 3, cc 1] xhci_trb_queue: ring 0xbf11eb00 [nidx 4, len 8] xhci_trb_queue: ring 0xbf11eb00 [nidx 5, len 9] xhci_trb_queue: ring 0xbf11eb00 [nidx 6, len 0] xhci_xfer_kick: ring 0xbf11eb00, slotid 1, epid 1 xhci_process_events: ring 0xbf11eb00 [trb 0xbf11eb50, evt 0xbf11ec00, type 32, eidx 6, cc 1] xhci_trb_queue: ring 0xbf11eb00 [nidx 7, len 8] xhci_trb_queue: ring 0xbf11eb00 [nidx 8, len 32] xhci_trb_queue: ring 0xbf11eb00 [nidx 9, len 0] xhci_xfer_kick: ring 0xbf11eb00, slotid 1, epid 1 xhci_process_events: ring 0xbf11eb00 [trb 0xbf11eb80, evt 0xbf11ec00, type 32, eidx 9, cc 1] xhci_trb_queue: ring 0xbf11eb00 [nidx 10, len 8] xhci_trb_queue: ring 0xbf11eb00 [nidx 11, len 0] xhci_xfer_kick: ring 0xbf11eb00, slotid 1, epid 1 xhci_process_events: ring 0xbf11eb00 [trb 0xbf11eba0, evt 0xbf11ec00, type 32, eidx 11, cc 1] xhci_alloc_pipe: usbdev 0xbf102530, ring 0x000ed400, slotid 1, epid 3 binterval=0 s0=f8300000 s1=00030000 e0=00000000 e1=02000030 xhci_cmd_configure_endpoint: slotid 1, add 0x9, del 0x0 xhci_trb_queue: ring 0xbf11ed00 [nidx 4, len 0] xhci_process_events: ring 0xbf11ed00 [trb 0xbf11ed30, evt 0xbf11ee00, type 33, eidx 4, cc 1] xhci_alloc_pipe: usbdev 0xbf102530, ring 0x000ed200, slotid 1, epid 4 binterval=0 s0=f8300000 s1=00030000 e0=00000000 e1=02000010 xhci_cmd_configure_endpoint: slotid 1, add 0x11, del 0x0 xhci_trb_queue: ring 0xbf11ed00 [nidx 5, len 0] xhci_process_events: ring 0xbf11ed00 [trb 0xbf11ed40, evt 0xbf11ee00, type 33, eidx 5, cc 1] xhci_trb_queue: ring 0xbf11eb00 [nidx 12, len 8] xhci_trb_queue: ring 0xbf11eb00 [nidx 13, len 1] xhci_trb_queue: ring 0xbf11eb00 [nidx 14, len 0] xhci_xfer_kick: ring 0xbf11eb00, slotid 1, epid 1 xhci_process_events: ring 0xbf11eb00 [trb 0xbf11ebd0, evt 0xbf11ec00, type 32, eidx 14, cc 1] Searching bootorder for: /pci@i0cf8/usb@10/storage@3/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@10/usb-*@3 xhci_trb_queue: ring 0x000ed200 [nidx 1, len 31] xhci_xfer_kick: ring 0x000ed200, slotid 1, epid 4 xhci_process_events: ring 0x000ed200 [trb 0x000ed200, evt 0x000ed300, type 32, eidx 1, cc 1] xhci_trb_queue: ring 0x000ed400 [nidx 1, len 36] xhci_xfer_kick: ring 0x000ed400, slotid 1, epid 3 xhci_process_events: ring 0x000ed400 [trb 0x000ed400, evt 0x000ed500, type 32, eidx 1, cc 1] xhci_trb_queue: ring 0x000ed400 [nidx 2, len 13] xhci_xfer_kick: ring 0x000ed400, slotid 1, epid 3 xhci_process_events: ring 0x000ed400 [trb 0x000ed410, evt 0x000ed500, type 32, eidx 2, cc 1] USB MSC vendor='Kingston' product='DataTraveler 2.0' rev='1.00' type=0 removable=1 scsi_is_ready (drive=0x000f4e90) xhci_trb_queue: ring 0x000ed200 [nidx 2, len 31] xhci_xfer_kick: ring 0x000ed200, slotid 1, epid 4 xhci_process_events: ring 0x000ed200 [trb 0x000ed210, evt 0x000ed300, type 32, eidx 2, cc 1] xhci_trb_queue: ring 0x000ed400 [nidx 3, len 13] xhci_xfer_kick: ring 0x000ed400, slotid 1, epid 3 xhci_process_events: ring 0x000ed400 [trb 0x000ed420, evt 0x000ed500, type 32, eidx 3, cc 1] xhci_trb_queue: ring 0x000ed200 [nidx 3, len 31] xhci_xfer_kick: ring 0x000ed200, slotid 1, epid 4 xhci_process_events: ring 0x000ed200 [trb 0x000ed220, evt 0x000ed300, type 32, eidx 3, cc 1] xhci_trb_queue: ring 0x000ed400 [nidx 4, len 8] xhci_xfer_kick: ring 0x000ed400, slotid 1, epid 3 xhci_process_events: ring 0x000ed400 [trb 0x000ed430, evt 0x000ed500, type 32, eidx 4, cc 1] xhci_trb_queue: ring 0x000ed400 [nidx 5, len 13] xhci_xfer_kick: ring 0x000ed400, slotid 1, epid 3 xhci_process_events: ring 0x000ed400 [trb 0x000ed440, evt 0x000ed500, type 32, eidx 5, cc 1] USB MSC blksize=512 sectors=1994752 Registering bootable: USB MSC Drive Kingston DataTraveler 2.0 1.00 (type:2 prio:103 data:f4e90) xhci_hub_detect port #4: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci hcc=14042c3 hcs=4000820 XHCI init on dev 00:10.1: regs @ 0xf014a000, 4 ports, 32 slots XHCI extcap 0x1 @ f014a500 XHCI protocol USB 3.00, 2 ports (offset 1) XHCI protocol USB 2.00, 2 ports (offset 3) configure_xhci: resetting xhci_hub_detect port #1: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #2: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #3: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #4: 0x000002a0, powered, pls 5, speed 0 [ - ] XHCI no devices found EHCI init on dev 00:12.2 (regs=0xf014f820) set_address 0xbf102480 ehci_alloc_async_pipe 0xbf102480 0 ehci_control 0xbf1021d0 (dir=0 cmd=8 data=0) ehci_alloc_async_pipe 0xbf102480 0 config_usb: 0xbf1021d0 ehci_control 0xbf1021d0 (dir=128 cmd=8 data=8) device rev=0200 cls=00 sub=00 proto=00 size=40 ehci_alloc_async_pipe 0xbf102480 0 ehci_control 0xbf1021d0 (dir=128 cmd=8 data=9) ehci_control 0xbf1021d0 (dir=128 cmd=8 data=46) OHCI init on dev 00:12.0 (regs=0xf014c000) set_address 0xbf1021e0 ohci_alloc_async_pipe 0xbf1021e0 ohci_control 0xbf102080 ohci_alloc_async_pipe 0xbf1021e0 config_usb: 0xbf102080 ohci_control 0xbf102080 device rev=0110 cls=00 sub=00 proto=00 size=08 ohci_alloc_async_pipe 0xbf1021e0 ohci_control 0xbf102080 ohci_control 0xbf102080 ohci_control 0xbf102080 usb_hid_setup 0xbf102080 ohci_control 0xbf102080 ohci_control 0xbf102080 ohci_alloc_intr_pipe 0xbf1021e0 3 USB keyboard initialized ohci_free_pipes 0xbf1021e0 ehci_free_pipes 0xbf102480 EHCI init on dev 00:13.2 (regs=0xf014f920) ehci_free_pipes 0xbf102480 OHCI init on dev 00:14.5 (regs=0xf014e000) ohci_free_pipes 0xbf102530
-Kevin
commit 5779c75cbea304d182a0291efd1f9422922200ce Author: Kevin O'Connor kevin@koconnor.net Date: Fri Dec 27 13:37:11 2013 -0500
xhci: Set the interval parameter on interrupt pipes. Be sure to set the interval parameter when creating an interrupt based pipe. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index d0df6ee..9d5449c 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -895,6 +895,8 @@ xhci_alloc_pipe(struct usbdevice_s *usbdev in->slot.ctx[0] |= (31 << 27); // context entries
int e = pipe->epid-1;
if (eptype == USB_ENDPOINT_XFER_INT)in->ep[e].ctx[0] = (usb_getFrameExp(usbdev, epdesc) + 3) << 16; in->ep[e].ctx[1] |= (eptype << 3); if (epdesc->bEndpointAddress & USB_DIR_IN) in->ep[e].ctx[1] |= (1 << 5);
-
Idwer Vollering -
Kevin O'Connor