Hi,
Seabios bits for q35 support, I'm posting the qemu changes separately. The patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the qemu command line. Hopefully, we can make it the default for x86 at some future point when we feel comfortable with it.
The current patches have been tested with basic install testing and memory testing on f16, f17, windows 7 and windows 8. They can be run on the various BSD flavors by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide. Patches have also been reported to work with a small dsdt change on OSX 10.6 as well.
I've dropped the ahci migration bits, which means q35 is not migratable at the moment. I simply haven't had time to make them more complete yet.
I'm hoping that we'll come to some agreement on the minimal functionality required for q35 to be merged.
Git trees:
git://github.com/jibaron/q35-qemu.git git://github.com/jibaron/q35-seabios.git
Notes:
I've dropped automatic load of the dsdt table on the piix for now. We can't pull this in until we have snapshot of the dsdt aml, and I wanted it to be done at a clean seabios freeze point (Although I guess that could be the current snapshot). I don't see the harm in pulling this in later though.
I've also gone to a model of the pci host being sparse:
00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller 00:01.0 VGA compatible controller: Cirrus Logic GD 5446 00:02.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03) 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02) 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)
The idea is only to populate the essential stuff at 1f, and have the rest filled out via command line options. In this way we have minimal bus configuration with 1 slot occupied as in piix. Should make things easier for libvirt. And this way user has complete control over things. For example, I have added support that when '-usb' is passed the usb controllers for ich9 are filled out.
Todo:
-add ahci migration back (need to cover more fields, but basically works) -add base addr for hpet in LPC device (for osx per agraf) -convert hotplug to use MemoryRegionPortio for hotplug (need an IsaDevice?)
Thanks,
-Jason
Changes from v2: -Patch restructure (broke out ich9 chips + data structures separately) -added passthrough support -add support for -usb to fill out host pci bus -Dropped automatic load of dsdt table for piix -cleanups -dropped wmask on smbus (mst) -sparse host bus
Changes from v1: -Updated end of low mem from 0xe0000000 -> 0xb0000000 (Gerd Hoffmann) -so 0xb000000-0xc000000 is memconfig -0xc000000-0xfec00000 is 32-bit pci window -style/various cleanups -introduced IF_AHCI -introduced mach_if -split dsdt out of bios, now passed for piix4 as well (Paolo, Gerd) -Removed add opaque argument to pci_map_irq_fn (Michael S. Tsirkin) -removed patches that were merged in v1
Isaku Yamahata (5): seabios: acpi: add mcfg table. seabios: acpi, fadt: make while fadt initialization chipset specific seabios: pci: enable SERR of normal device. seabios: add q35 initialization functions. seabios: q35: add dsdt
Jan Kiszka (1): seabios: q35: Register PCI IRQs as active high in APIC mode
Jason Baron (2): seabios: make mttr UC area setup dynamic seabios: q35: add basic hotplug support
Makefile | 2 +- src/acpi.c | 176 ++++++++- src/acpi.h | 17 + src/config.h | 1 - src/dev-q35.h | 46 +++ src/mtrr.c | 5 +- src/pci.h | 1 + src/pciinit.c | 87 +++++- src/post.c | 6 +- src/q35-acpi-dsdt.dsl | 980 +++++++++++++++++++++++++++++++++++++++++++++++++ src/shadow.c | 13 + src/smm.c | 37 ++ 12 files changed, 1344 insertions(+), 27 deletions(-) create mode 100644 src/dev-q35.h create mode 100644 src/q35-acpi-dsdt.dsl
From: Jason Baron jbaron@redhat.com
Set up the UC area of mtrr dynamically based on mtrr_base. This allows the bios to work for other chipsets that might want to set the mtrr. Since BUILD_MAX_HIGHMEM is no longer used we can remove the config parameter.
This change reverses the order of pci_setup() and smm_init() with mtrr_setup().
Signed-off-by: Jason Baron jbaron@redhat.com --- src/config.h | 1 - src/mtrr.c | 5 +++-- src/pci.h | 1 + src/pciinit.c | 2 ++ src/post.c | 6 +++--- 5 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/src/config.h b/src/config.h index 0d4066d..71c0b7e 100644 --- a/src/config.h +++ b/src/config.h @@ -44,7 +44,6 @@ #define BUILD_SMM_INIT_ADDR 0x38000 #define BUILD_SMM_ADDR 0xa8000 #define BUILD_SMM_SIZE 0x8000 -#define BUILD_MAX_HIGHMEM 0xe0000000
#define BUILD_PCIMEM_START 0xe0000000 #define BUILD_PCIMEM_END 0xfec00000 /* IOAPIC is mapped at */ diff --git a/src/mtrr.c b/src/mtrr.c index 0957834..81a78c6 100644 --- a/src/mtrr.c +++ b/src/mtrr.c @@ -7,6 +7,7 @@ #include "util.h" // dprintf #include "config.h" // CONFIG_* #include "xen.h" // usingXen +#include "pci.h" // mtrr_base
#define MSR_MTRRcap 0x000000fe #define MSR_MTRRfix64K_00000 0x00000250 @@ -94,9 +95,9 @@ void mtrr_setup(void) wrmsr_smp(MTRRphysMask_MSR(i), 0); } /* Mark 3.5-4GB as UC, anything not specified defaults to WB */ - wrmsr_smp(MTRRphysBase_MSR(0), BUILD_MAX_HIGHMEM | MTRR_MEMTYPE_UC); + wrmsr_smp(MTRRphysBase_MSR(0), mtrr_base | MTRR_MEMTYPE_UC); wrmsr_smp(MTRRphysMask_MSR(0) - , (-((1ull<<32)-BUILD_MAX_HIGHMEM) & phys_mask) | 0x800); + , (-((1ull<<32)-mtrr_base) & phys_mask) | 0x800);
// Enable fixed and variable MTRRs; set default type. wrmsr_smp(MSR_MTRRdefType, 0xc00 | MTRR_MEMTYPE_WB); diff --git a/src/pci.h b/src/pci.h index fe663b8..104638d 100644 --- a/src/pci.h +++ b/src/pci.h @@ -56,6 +56,7 @@ struct pci_device { // Local information on device. int have_driver; }; +extern u64 mtrr_base; extern u64 pcimem_start, pcimem_end; extern u64 pcimem64_start, pcimem64_end; extern struct pci_device *PCIDevices; diff --git a/src/pciinit.c b/src/pciinit.c index 31115ee..0b4a9e4 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -30,6 +30,8 @@ static const char *region_type_name[] = { [ PCI_REGION_TYPE_PREFMEM ] = "prefmem", };
+u64 mtrr_base = BUILD_PCIMEM_START; + u64 pcimem_start = BUILD_PCIMEM_START; u64 pcimem_end = BUILD_PCIMEM_END; u64 pcimem64_start = BUILD_PCIMEM64_START; diff --git a/src/post.c b/src/post.c index 924b311..c976c8e 100644 --- a/src/post.c +++ b/src/post.c @@ -231,13 +231,13 @@ maininit(void) timer_setup(); mathcp_setup();
- // Initialize mtrr - mtrr_setup(); - // Initialize pci pci_setup(); smm_init();
+ // Initialize mtrr + mtrr_setup(); + // Setup Xen hypercalls xen_init_hypercalls();
From: Isaku Yamahata yamahata@valinux.co.jp
add mcfg table. mcfg isn't populated at the moment. dev-q35 will use it later.
[jbaron@redhat.com: moved header from post.h -> acpi.h] Reviewed-by: Paolo Bonzini pbonzini@redhat.com Signed-off-by: Isaku Yamahata yamahata@valinux.co.jp Signed-off-by: Jason Baron jbaron@redhat.com --- src/acpi.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/acpi.h | 17 ++++++++++++++ 2 files changed, 89 insertions(+), 0 deletions(-)
diff --git a/src/acpi.c b/src/acpi.c index 6d239fa..eff191d 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -13,6 +13,7 @@ #include "pci_regs.h" // PCI_INTERRUPT_LINE #include "ioport.h" // inl #include "paravirt.h" // qemu_cfg_irq0_override +#include "memmap.h"
/****************************************************/ /* ACPI tables init */ @@ -734,6 +735,76 @@ build_srat(void) return srat; }
+struct acpi_mcfg { + u32 nr; + struct acpi_table_mcfg *mcfg; + struct e820entry *e820; +}; + +static const struct pci_device_id mcfg_find_tbl[] = { + PCI_DEVICE_END, +}; + +static const struct pci_device_id mcfg_init_tbl[] = { + PCI_DEVICE_END, +}; + +static void * +build_mcfg(void) +{ + struct pci_device *dev; + int bdf; + + struct acpi_mcfg acpi_mcfg = { + .nr = 0, + .mcfg = NULL, + .e820 = NULL, + }; + dev = pci_find_init_device(mcfg_find_tbl, &acpi_mcfg); + bdf = dev->bdf; + if (bdf < 0) { + return NULL; + } + if (acpi_mcfg.nr == 0) { + return NULL; + } + + struct acpi_table_mcfg *mcfg; + int len = sizeof(*mcfg) + acpi_mcfg.nr * sizeof(mcfg->allocation[0]); + mcfg = malloc_high(len); + if (!mcfg) { + dprintf(1, "Not enough memory for mcfg table!\n"); + return NULL; + } + memset(mcfg, 0, len); + acpi_mcfg.mcfg = mcfg; + + + struct e820entry *e820; + int e820_len = acpi_mcfg.nr * sizeof(*e820); + e820 = malloc_tmphigh(e820_len); + if (!e820) { + dprintf(1, "Not enough memory for e820 table!\n"); + free(mcfg); + return NULL; + } + memset(e820, 0, e820_len); + acpi_mcfg.e820 = e820; + + pci_init_device(mcfg_init_tbl, dev, &acpi_mcfg); + + /* Linux checks if e820 covers mcfg area as reserved. + * If no, Linux thinks bios is buggy and won't use MCFG */ + int i; + for (i = 0; i < acpi_mcfg.nr; i++) { + add_e820(e820[i].start, e820[i].size, E820_RESERVED); + } + free(e820); + + build_header((void *)mcfg, MCFG_SIGNATURE, len, 1); + return mcfg; +} + static const struct pci_device_id acpi_find_tbl[] = { /* PIIX4 Power Management device. */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL), @@ -774,6 +845,7 @@ acpi_bios_init(void) ACPI_INIT_TABLE(build_madt()); ACPI_INIT_TABLE(build_hpet()); ACPI_INIT_TABLE(build_srat()); + ACPI_INIT_TABLE(build_mcfg());
u16 i, external_tables = qemu_cfg_acpi_additional_tables();
diff --git a/src/acpi.h b/src/acpi.h index cb21561..715d19d 100644 --- a/src/acpi.h +++ b/src/acpi.h @@ -107,4 +107,21 @@ struct bfld { u64 p1l; /* pci window 1 (above 4g) - length */ } PACKED;
+/* PCI fw r3.0 MCFG table. */ +/* Subtable */ +struct acpi_mcfg_allocation { + u64 address; /* Base address, processor-relative */ + u16 pci_segment; /* PCI segment group number */ + u8 start_bus_number; /* Starting PCI Bus number */ + u8 end_bus_number; /* Final PCI Bus number */ + u32 reserved; +} PACKED; + +#define MCFG_SIGNATURE 0x4746434d // MCFG +struct acpi_table_mcfg { + ACPI_TABLE_HEADER_DEF; + u8 reserved[8]; + struct acpi_mcfg_allocation allocation[0]; +} PACKED; + #endif // acpi.h
From: Isaku Yamahata yamahata@valinux.co.jp
make while fadt initialization chipset specific.
Reviewed-by: Paolo Bonzini pbonzini@redhat.com Signed-off-by: Isaku Yamahata yamahata@valinux.co.jp Signed-off-by: Jason Baron jbaron@redhat.com --- src/acpi.c | 34 ++++++++++++++++++---------------- 1 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/src/acpi.c b/src/acpi.c index eff191d..60a22f5 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -234,13 +234,31 @@ build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev) #define PIIX4_GPE0_BLK 0xafe0 #define PIIX4_GPE0_BLK_LEN 4
+#define PIIX4_PM_INTRRUPT 9 // irq 9 + static void piix4_fadt_init(struct pci_device *pci, void *arg) { struct fadt_descriptor_rev1 *fadt = arg; + + fadt->model = 1; + fadt->reserved1 = 0; + fadt->sci_int = cpu_to_le16(PIIX4_PM_INTRRUPT); + fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD); fadt->acpi_enable = PIIX4_ACPI_ENABLE; fadt->acpi_disable = PIIX4_ACPI_DISABLE; + fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE); + fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04); + fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08); fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK); + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN; + fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported + fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported + /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */ + fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) | + (1 << 15)); }
static const struct pci_device_id fadt_init_tbl[] = { @@ -282,23 +300,7 @@ build_fadt(struct pci_device *pci) fadt->firmware_ctrl = cpu_to_le32((u32)facs); fadt->dsdt = 0; /* dsdt will be filled later in acpi_bios_init() by fill_dsdt() */ - fadt->model = 1; - fadt->reserved1 = 0; - int pm_sci_int = pci_config_readb(pci->bdf, PCI_INTERRUPT_LINE); - fadt->sci_int = cpu_to_le16(pm_sci_int); - fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD); - fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE); - fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04); - fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08); - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm_tmr_len = 4; - fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported - fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported pci_init_device(fadt_init_tbl, pci, fadt); - /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */ - fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) | - (1 << 15));
build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
From: Isaku Yamahata yamahata@valinux.co.jp
add q35 initialization functions.
[jbaron@redhat.com: restructured to current seabios base, updated pci base to 0xb0000000] Signed-off-by: Isaku Yamahata yamahata@valinux.co.jp Signed-off-by: Jason Baron jbaron@redhat.com --- src/acpi.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++- src/dev-q35.h | 46 ++++++++++++++++++++++++++++++++ src/pciinit.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- src/shadow.c | 13 +++++++++ src/smm.c | 37 +++++++++++++++++++++++++ 5 files changed, 245 insertions(+), 3 deletions(-) create mode 100644 src/dev-q35.h
diff --git a/src/acpi.c b/src/acpi.c index 60a22f5..4f6a0c5 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -14,6 +14,7 @@ #include "ioport.h" // inl #include "paravirt.h" // qemu_cfg_irq0_override #include "memmap.h" +#include "dev-q35.h"
/****************************************************/ /* ACPI tables init */ @@ -261,11 +262,38 @@ static void piix4_fadt_init(struct pci_device *pci, void *arg) (1 << 15)); }
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */ +void ich9_lpc_fadt_init(struct pci_device *dev, void *arg) +{ + struct fadt_descriptor_rev1 *fadt = arg; + + fadt->model = 1; + fadt->reserved1 = 0; + fadt->sci_int = cpu_to_le16(9); + fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD); + fadt->acpi_enable = ICH9_ACPI_ENABLE; + fadt->acpi_disable = ICH9_ACPI_DISABLE; + fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE); + fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04); + fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08); + fadt->gpe0_blk = cpu_to_le32(PORT_ACPI_PM_BASE + ICH9_PMIO_GPE0_STS); + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = ICH9_PMIO_GPE0_BLK_LEN; + fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported + fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported + /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC + RTC_S4 */ + fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6) | + (1 << 7)); +} + static const struct pci_device_id fadt_init_tbl[] = { /* PIIX4 Power Management device (for ACPI) */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, piix4_fadt_init), - + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, + ich9_lpc_fadt_init), PCI_DEVICE_END };
@@ -743,11 +771,49 @@ struct acpi_mcfg { struct e820entry *e820; };
+/* PCI_VENDOR_ID_INTEL && DEVICE_ID_INTEL_Q35_MCH */ +void mch_mcfg_find(struct pci_device *dev, void *arg) +{ + struct acpi_mcfg *mcfg = arg; + + mcfg->nr = 1; +} + +/* PCI_VENDOR_ID_INTEL && DEVICE_ID_INTEL_Q35_MCH */ +void mch_mcfg_init(struct pci_device *dev, void *arg) +{ + u16 bdf = dev->bdf; + + u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR | Q35_HOST_BRIDGE_PCIEXBAREN; + u32 upper = addr >> 32; + u32 lower = addr & 0xffffffff; + + /* at first disable the region. and then update/enable it. */ + pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0); + pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper); + pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower); + + struct acpi_mcfg *mcfg = arg; + struct acpi_mcfg_allocation *alloc = &mcfg->mcfg->allocation[0]; + alloc->address = Q35_HOST_BRIDGE_PCIEXBAR_ADDR; + alloc->pci_segment = Q35_HOST_PCIE_PCI_SEGMENT; + alloc->start_bus_number = Q35_HOST_PCIE_START_BUS_NUMBER; + alloc->end_bus_number = Q35_HOST_PCIE_END_BUS_NUMBER; + + mcfg->e820->start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR; + mcfg->e820->size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE; + mcfg->e820->type = E820_RESERVED; +} + static const struct pci_device_id mcfg_find_tbl[] = { + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH, + mch_mcfg_find), PCI_DEVICE_END, };
static const struct pci_device_id mcfg_init_tbl[] = { + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH, + mch_mcfg_init), PCI_DEVICE_END, };
@@ -810,7 +876,7 @@ build_mcfg(void) static const struct pci_device_id acpi_find_tbl[] = { /* PIIX4 Power Management device. */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL), - + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, NULL), PCI_DEVICE_END, };
diff --git a/src/dev-q35.h b/src/dev-q35.h new file mode 100644 index 0000000..6ae039f --- /dev/null +++ b/src/dev-q35.h @@ -0,0 +1,46 @@ +#ifndef __DEV_Q35_H +#define __DEV_Q35_H + +#include "types.h" // u16 + +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 +#define Q35_HOST_BRIDGE_PAM0 0x90 +#define Q35_HOST_BRIDGE_SMRAM 0x9d +#define Q35_HOST_BRIDGE_PCIEXBAR 0x60 +#define Q35_HOST_BRIDGE_PCIEXBAR_SIZE (256 * 1024 * 1024) +#define Q35_HOST_BRIDGE_PCIEXBAR_ADDR 0xb0000000 +#define Q35_HOST_BRIDGE_PCIEXBAREN ((u64)1) +#define Q35_HOST_PCIE_PCI_SEGMENT 0 +#define Q35_HOST_PCIE_START_BUS_NUMBER 0 +#define Q35_HOST_PCIE_END_BUS_NUMBER 255 + +#define PCI_DEVICE_ID_INTEL_ICH9_LPC 0x2918 +#define ICH9_LPC_PMBASE 0x40 +#define ICH9_LPC_PMBASE_RTE 0x1 + +#define ICH9_LPC_ACPI_CTRL 0x44 +#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 +#define ICH9_LPC_PIRQA_ROUT 0x60 +#define ICH9_LPC_PIRQE_ROUT 0x68 +#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 +#define ICH9_LPC_PORT_ELCR1 0x4d0 +#define ICH9_LPC_PORT_ELCR2 0x4d1 +#define PCI_DEVICE_ID_INTEL_ICH9_SMBUS 0x2930 +#define ICH9_SMB_SMB_BASE 0x20 +#define ICH9_SMB_HOSTC 0x40 +#define ICH9_SMB_HOSTC_HST_EN 0x01 + +#define ICH9_ACPI_ENABLE 0x2 +#define ICH9_ACPI_DISABLE 0x3 + +/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ +#define ICH9_PMIO_GPE0_STS 0x20 +#define ICH9_PMIO_GPE0_BLK_LEN 0x10 +#define ICH9_PMIO_SMI_EN 0x30 +#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) + +/* FADT ACPI_ENABLE/ACPI_DISABLE */ +#define ICH9_APM_ACPI_ENABLE 0x2 +#define ICH9_APM_ACPI_DISABLE 0x3 + +#endif // dev-q35.h diff --git a/src/pciinit.c b/src/pciinit.c index 7e76379..93a53e8 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -12,6 +12,7 @@ #include "ioport.h" // PORT_ATA1_CMD_BASE #include "config.h" // CONFIG_* #include "xen.h" // usingXen +#include "dev-q35.h" // usingXen
#define PCI_DEVICE_MEM_MIN 0x1000 #define PCI_BRIDGE_IO_MIN 0x1000 @@ -121,12 +122,44 @@ static void piix_isa_bridge_init(struct pci_device *pci, void *arg) dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]); }
+/* ICH9 LPC PCI to ISA bridge */ +/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */ +void mch_isa_bridge_init(struct pci_device *dev, void *arg) +{ + u16 bdf = dev->bdf; + int i, irq; + u8 elcr[2]; + + elcr[0] = 0x00; + elcr[1] = 0x00; + + for (i = 0; i < 4; i++) { + irq = pci_irqs[i]; + /* set to trigger level */ + elcr[irq >> 3] |= (1 << (irq & 7)); + + /* activate irq remapping in LPC */ + + /* PIRQ[A-D] routing */ + pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, + irq | ICH9_LPC_PIRQ_ROUT_IRQEN); + /* PIRQ[E-H] routing */ + pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, + irq | ICH9_LPC_PIRQ_ROUT_IRQEN); + } + outb(elcr[0], ICH9_LPC_PORT_ELCR1); + outb(elcr[1], ICH9_LPC_PORT_ELCR2); + dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]); +} + static const struct pci_device_id pci_isa_bridge_tbl[] = { /* PIIX3/PIIX4 PCI to ISA bridge */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, piix_isa_bridge_init), PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, piix_isa_bridge_init), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, + mch_isa_bridge_init),
PCI_DEVICE_END }; @@ -200,11 +233,40 @@ static void piix4_pm_init(struct pci_device *pci, void *arg) pmtimer_init(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000); }
+/* ICH9 LPC Power Management device (for ACPI) */ +/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */ +void ich9_lpc_pm_init(struct pci_device *dev, void *arg) +{ + u16 bdf = dev->bdf; + /* pm io base */ + pci_config_writel(bdf, ICH9_LPC_PMBASE, + PORT_ACPI_PM_BASE | ICH9_LPC_PMBASE_RTE); + + /* acpi enable, SCI: IRQ9 000b = irq9*/ + pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN); +} + +/* ICH9 SMBUS */ +/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */ +void ich9_smbus_init(struct pci_device *dev, void *arg) +{ + u16 bdf = dev->bdf; + /* map smbus into io space */ + pci_config_writel(bdf, ICH9_SMB_SMB_BASE, + PORT_SMB_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* enable SMBus */ + pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN); +} + static const struct pci_device_id pci_device_tbl[] = { /* PIIX4 Power Management device (for ACPI) */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, piix4_pm_init), - + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, + ich9_lpc_pm_init), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS, + ich9_smbus_init), PCI_DEVICE_END, };
@@ -598,10 +660,28 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) } }
+void mch_mem_addr_init(struct pci_device *dev, void *arg) +{ + u64 *start = (u64 *)arg; + /* mmconfig space */ + *start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR + + Q35_HOST_BRIDGE_PCIEXBAR_SIZE; + mtrr_base = *start; +} + +static const struct pci_device_id pci_mem_addr_tbl[] = { + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH, + mch_mem_addr_init), + PCI_DEVICE_END, +}; + static void pci_bios_map_devices(struct pci_bus *busses) { pcimem_start = RamSize;
+ /* let's add in mmconfig space on q35 */ + pci_find_init_device(pci_mem_addr_tbl, &pcimem_start); + if (pci_bios_init_root_regions(busses)) { struct pci_region r64_mem, r64_pref; r64_mem.list = NULL; diff --git a/src/shadow.c b/src/shadow.c index 11c4d5e..a2195da 100644 --- a/src/shadow.c +++ b/src/shadow.c @@ -11,6 +11,7 @@ #include "pci_ids.h" // PCI_VENDOR_ID_INTEL #include "pci_regs.h" // PCI_VENDOR_ID #include "xen.h" // usingXen +#include "dev-q35.h" // PCI_VENDOR_ID_INTEL
// On the emulators, the bios at 0xf0000 is also at 0xffff0000 #define BIOS_SRC_OFFSET 0xfff00000 @@ -101,9 +102,16 @@ static void i440fx_bios_make_readonly(struct pci_device *pci, void *arg) make_bios_readonly_intel(pci->bdf, I440FX_PAM0); }
+void mch_bios_make_readonly(struct pci_device *pci, void *arg) +{ + make_bios_readonly_intel(pci->bdf, Q35_HOST_BRIDGE_PAM0); +} + static const struct pci_device_id dram_controller_make_readonly_tbl[] = { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, i440fx_bios_make_readonly), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH, + mch_bios_make_readonly), PCI_DEVICE_END };
@@ -127,6 +135,11 @@ make_bios_writable(void) make_bios_writable_intel(bdf, I440FX_PAM0); return; } + if (vendor == PCI_VENDOR_ID_INTEL + && device == PCI_DEVICE_ID_INTEL_Q35_MCH) { + make_bios_writable_intel(bdf, Q35_HOST_BRIDGE_PAM0); + return; + } } dprintf(1, "Unable to unlock ram - bridge not found\n"); } diff --git a/src/smm.c b/src/smm.c index d0d1476..7977ac7 100644 --- a/src/smm.c +++ b/src/smm.c @@ -11,6 +11,7 @@ #include "ioport.h" // outb #include "pci_ids.h" // PCI_VENDOR_ID_INTEL #include "xen.h" // usingXen +#include "dev-q35.h"
ASM32FLAT( ".global smm_relocation_start\n" @@ -137,9 +138,45 @@ static void piix4_apmc_smm_init(struct pci_device *pci, void *arg) pci_config_writeb(i440_pci->bdf, I440FX_SMRAM, 0x02 | 0x08); }
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */ +void ich9_lpc_apmc_smm_init(struct pci_device *dev, void *arg) +{ + struct pci_device *mch_dev; + int mch_bdf; + + // This code is hardcoded for Q35 Power Management device. + mch_dev = pci_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_Q35_MCH); + mch_bdf = mch_dev->bdf; + + if (mch_bdf < 0) + return; + + /* check if SMM init is already done */ + u32 value = inl(PORT_ACPI_PM_BASE + ICH9_PMIO_SMI_EN); + if (value & ICH9_PMIO_SMI_EN_APMC_EN) + return; + + /* enable the SMM memory window */ + pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x48); + + smm_save_and_copy(); + + /* enable SMI generation when writing to the APMC register */ + outl(value | ICH9_PMIO_SMI_EN_APMC_EN, + PORT_ACPI_PM_BASE + ICH9_PMIO_SMI_EN); + + smm_relocate_and_restore(); + + /* close the SMM memory window and enable normal SMM */ + pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x08); +} + static const struct pci_device_id smm_init_tbl[] = { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, piix4_apmc_smm_init), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, + ich9_lpc_apmc_smm_init),
PCI_DEVICE_END, };
From: Isaku Yamahata yamahata@valinux.co.jp
enable SERR of normal device for AER.
Reviewed-by: Paolo Bonzini pbonzini@redhat.com Signed-off-by: Isaku Yamahata yamahata@valinux.co.jp Signed-off-by: Jason Baron jbaron@redhat.com --- src/pciinit.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/pciinit.c b/src/pciinit.c index 0b4a9e4..7e76379 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -218,7 +218,8 @@ static void pci_bios_init_device(struct pci_device *pci) pci_init_device(pci_class_tbl, pci, NULL);
/* enable memory mappings */ - pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + pci_config_maskw(bdf, PCI_COMMAND, 0, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
/* map the interrupt */ int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
From: Isaku Yamahata yamahata@valinux.co.jp
add dsdt for q35 chipset of qemu.
[jbaron: remove suspd bits since they are now auto-generated, move pci window to 0xb0000000, add framework for auto generated pci windows] Cc: Matthew Garrett mjg59@srcf.ucam.org Signed-off-by: Isaku Yamahata yamahata@valinux.co.jp Signed-off-by: Jason Baron jbaron@redhat.com --- Makefile | 2 +- src/q35-acpi-dsdt.dsl | 909 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 910 insertions(+), 1 deletions(-) create mode 100644 src/q35-acpi-dsdt.dsl
diff --git a/Makefile b/Makefile index 5486f88..79abab6 100644 --- a/Makefile +++ b/Makefile @@ -233,7 +233,7 @@ $(OUT)%.hex: src/%.dsl ./tools/acpi_extract_preprocess.py ./tools/acpi_extract.p $(Q)$(PYTHON) ./tools/acpi_extract.py $(OUT)$*.lst > $(OUT)$*.off $(Q)cat $(OUT)$*.off > $@
-$(OUT)ccode32flat.o: $(OUT)acpi-dsdt.hex $(OUT)ssdt-proc.hex $(OUT)ssdt-pcihp.hex $(OUT)ssdt-susp.hex +$(OUT)ccode32flat.o: $(OUT)acpi-dsdt.hex $(OUT)ssdt-proc.hex $(OUT)ssdt-pcihp.hex $(OUT)ssdt-susp.hex $(OUT)q35-acpi-dsdt.hex
################ Kconfig rules
diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl new file mode 100644 index 0000000..c9fa5c6 --- /dev/null +++ b/src/q35-acpi-dsdt.dsl @@ -0,0 +1,909 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* + * Copyright (c) 2010 Isaku Yamahata + * yamahata at valinux co jp + * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset. + */ + +DefinitionBlock ( + "q35-acpi-dsdt.aml",// Output Filename + "DSDT", // Signature + 0x01, // DSDT Compliance Revision + "BXPC", // OEMID + "BXDSDT", // TABLE ID + 0x2 // OEM Revision + ) +{ + Scope () + { + /* Debug Output */ + OperationRegion (DBG, SystemIO, 0x0402, 0x01) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8, + } + + /* Debug method - use this method to send output to the QEMU + * BIOS debug port. This method handles strings, integers, + * and buffers. For example: DBUG("abc") DBUG(0x123) */ + Method(DBUG, 1) { + ToHexString(Arg0, Local0) + ToBuffer(Local0, Local0) + Subtract(SizeOf(Local0), 1, Local1) + Store(Zero, Local2) + While (LLess(Local2, Local1)) { + Store(DerefOf(Index(Local0, Local2)), DBGB) + Increment(Local2) + } + Store(0x0A, DBGB) + } + } + + + Scope (_SB) + { + OperationRegion(PCST, SystemIO, 0xae00, 0x0c) + OperationRegion(PCSB, SystemIO, 0xae0c, 0x01) + Field (PCSB, AnyAcc, NoLock, WriteAsZeros) + { + PCIB, 8, + } + } + + /* Zero => PIC mode, One => APIC Mode */ + Name (\PICF, Zero) + Method (_PIC, 1, NotSerialized) + { + Store (Arg0, \PICF) + } + + /* PCI Bus definition */ + Scope(_SB) { + + Device(PCI0) { + Name (_HID, EisaId ("PNP0A08")) + Name (_CID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 1) + + // _OSC: based on sample of ACPI3.0b spec + Name(SUPP,0) // PCI _OSC Support Field value + Name(CTRL,0) // PCI _OSC Control Field value + Method(_OSC,4) + { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWORD2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + +#if 0 // For now, nothing to do + If(Not(And(CDW1,1))) // Query flag clear? + { // Disable GPEs for features granted native control. + If(And(CTRL,0x01)) // Hot plug control granted? + { + Store(0,HPCE) // clear the hot plug SCI enable bit + Store(1,HPCS) // clear the hot plug SCI status bit + } + If(And(CTRL,0x04)) // PME control granted? + { + Store(0,PMCE) // clear the PME SCI enable bit + Store(1,PMCS) // clear the PME SCI status bit + } + If(And(CTRL,0x10)) // OS restoring PCI Express cap structure? + { + // Set status to not restore PCI Express cap structure + // upon resume from S3 + Store(1,S3CR) + } + + } +#endif + If(LNotEqual(Arg1,One)) + { // Unknown revision + Or(CDW1,0x08,CDW1) + } + If(LNotEqual(CDW3,CTRL)) + { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + } + Return(Arg3) + } + +#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \ + Package() { nr##ffff, 0, lnk0, 0 }, \ + Package() { nr##ffff, 1, lnk1, 0 }, \ + Package() { nr##ffff, 2, lnk2, 0 }, \ + Package() { nr##ffff, 3, lnk3, 0 } + +#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD) +#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA) +#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB) +#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC) + +#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH) +#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE) +#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF) +#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG) + +#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \ + Package() { nr##ffff, 0, 0, gsi0 }, \ + Package() { nr##ffff, 1, 0, gsi1 }, \ + Package() { nr##ffff, 2, 0, gsi2 }, \ + Package() { nr##ffff, 3, 0, gsi3 } + +#define GSIA 0x10 +#define GSIB 0x11 +#define GSIC 0x12 +#define GSID 0x13 +#define GSIE 0x14 +#define GSIF 0x15 +#define GSIG 0x16 +#define GSIH 0x17 + +#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID) +#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA) +#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB) +#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC) + +#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH) +#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE) +#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF) +#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG) + + NAME(PRTP, package() + { + prt_slot_lnkE(0x0000), + prt_slot_lnkF(0x0001), + prt_slot_lnkG(0x0002), + prt_slot_lnkH(0x0003), + prt_slot_lnkE(0x0004), + prt_slot_lnkF(0x0005), + prt_slot_lnkG(0x0006), + prt_slot_lnkH(0x0007), + prt_slot_lnkE(0x0008), + prt_slot_lnkF(0x0009), + prt_slot_lnkG(0x000a), + prt_slot_lnkH(0x000b), + prt_slot_lnkE(0x000c), + prt_slot_lnkF(0x000d), + prt_slot_lnkG(0x000e), + prt_slot_lnkH(0x000f), + prt_slot_lnkE(0x0010), + prt_slot_lnkF(0x0011), + prt_slot_lnkG(0x0012), + prt_slot_lnkH(0x0013), + prt_slot_lnkE(0x0014), + prt_slot_lnkF(0x0015), + prt_slot_lnkG(0x0016), + prt_slot_lnkH(0x0017), + prt_slot_lnkE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31 + see the default value of D<N>IR */ + prt_slot_lnkA(0x0019), + prt_slot_lnkA(0x001a), + prt_slot_lnkA(0x001b), + prt_slot_lnkA(0x001c), + prt_slot_lnkA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_lnkE(0x001e), + + prt_slot_lnkA(0x001f) + }) + + NAME(PRTA, package() + { + prt_slot_gsiE(0x0000), + prt_slot_gsiF(0x0001), + prt_slot_gsiG(0x0002), + prt_slot_gsiH(0x0003), + prt_slot_gsiE(0x0004), + prt_slot_gsiF(0x0005), + prt_slot_gsiG(0x0006), + prt_slot_gsiH(0x0007), + prt_slot_gsiE(0x0008), + prt_slot_gsiF(0x0009), + prt_slot_gsiG(0x000a), + prt_slot_gsiH(0x000b), + prt_slot_gsiE(0x000c), + prt_slot_gsiF(0x000d), + prt_slot_gsiG(0x000e), + prt_slot_gsiH(0x000f), + prt_slot_gsiE(0x0010), + prt_slot_gsiF(0x0011), + prt_slot_gsiG(0x0012), + prt_slot_gsiH(0x0013), + prt_slot_gsiE(0x0014), + prt_slot_gsiF(0x0015), + prt_slot_gsiG(0x0016), + prt_slot_gsiH(0x0017), + prt_slot_gsiE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31, but 30 + see the default value of D<N>IR */ + prt_slot_gsiA(0x0019), + prt_slot_gsiA(0x001a), + prt_slot_gsiA(0x001b), + prt_slot_gsiA(0x001c), + prt_slot_gsiA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_gsiE(0x001e), + + prt_slot_gsiA(0x001f) + }) + + Method(_PRT, 0, NotSerialized) + { + /* PCI IRQ routing table, example from ACPI 2.0a specification, + section 6.2.8.1 */ + /* Note: we provide the same info as the PCI routing + table of the Bochs BIOS */ + If (LEqual (\PICF, Zero)) + { + Return (PRTP) + } + Else + { + Return (PRTA) + } + } + + Name (CRES, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x00FF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0100, // Address Length + ,, ) + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0D00, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0xF300, // Address Length + ,, , TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000A0000, // Address Range Minimum + 0x000BFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00020000, // Address Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0xC0000000, // Address Range Minimum + 0xFEBFFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x3EC00000, // Address Length + ,, PW32, AddressRangeMemory, TypeStatic) + }) + Name (CR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x8000000000, // Address Range Minimum + 0xFFFFFFFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x8000000000, // Address Length + ,, PW64, AddressRangeMemory, TypeStatic) + }) + Method (_CRS, 0) + { + /* see see acpi.h, struct bfld */ + External (BDAT, OpRegionObj) + Field(BDAT, QWordAcc, NoLock, Preserve) { + P0S, 64, + P0E, 64, + P0L, 64, + P1S, 64, + P1E, 64, + P1L, 64, + } + Field(BDAT, DWordAcc, NoLock, Preserve) { + P0SL, 32, + P0SH, 32, + P0EL, 32, + P0EH, 32, + P0LL, 32, + P0LH, 32, + P1SL, 32, + P1SH, 32, + P1EL, 32, + P1EH, 32, + P1LL, 32, + P1LH, 32, + } + + /* fixup 32bit pci io window */ + CreateDWordField (CRES,_SB.PCI0.PW32._MIN, PS32) + CreateDWordField (CRES,_SB.PCI0.PW32._MAX, PE32) + CreateDWordField (CRES,_SB.PCI0.PW32._LEN, PL32) + Store (P0SL, PS32) + Store (P0EL, PE32) + Store (P0LL, PL32) + + If (LAnd(LEqual(P1SL, 0x00), LEqual(P1SH, 0x00))) { + Return (CRES) + } Else { + /* fixup 64bit pci io window */ + CreateQWordField (CR64,_SB.PCI0.PW64._MIN, PS64) + CreateQWordField (CR64,_SB.PCI0.PW64._MAX, PE64) + CreateQWordField (CR64,_SB.PCI0.PW64._LEN, PL64) + Store (P1S, PS64) + Store (P1E, PE64) + Store (P1L, PL64) + /* add window and return result */ + ConcatenateResTemplate (CRES, CR64, Local0) + Return (Local0) + } + } + } + } + + Scope(_SB.PCI0) { + Device (VGA) { + Name (_ADR, 0x00020000) + Method (_S1D, 0, NotSerialized) + { + Return (0x00) + } + Method (_S2D, 0, NotSerialized) + { + Return (0x00) + } + Method (_S3D, 0, NotSerialized) + { + Return (0x00) + } + } + + + /* PCI D31:f0 LPC ISA bridge */ + Device (LPC) { + /* PCI D31:f0 */ + Name (_ADR, 0x001f0000) + + /* ICH9 PCI to ISA irq remapping */ + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + Field (PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + OperationRegion (LPCD, PCI_Config, 0x80, 0x2) + Field (LPCD, AnyAcc, NoLock, Preserve) + { + COMA, 3, + , 1, + COMB, 3, + + Offset(0x01), + LPTD, 2, + , 2, + FDCD, 2 + } + OperationRegion (LPCE, PCI_Config, 0x82, 0x2) + Field (LPCE, AnyAcc, NoLock, Preserve) + { + CAEN, 1, + CBEN, 1, + LPEN, 1, + FDEN, 1 + } + + /* High Precision Event Timer */ + Device(HPET) { + Name(_HID, EISAID("PNP0103")) + Name(_UID, 0) + Method (_STA, 0, NotSerialized) { + Return(0x0F) + } + Name(_CRS, ResourceTemplate() { + DWordMemory( + ResourceConsumer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, + 0xFED00000, + 0xFED003FF, + 0x00000000, + 0x00000400 /* 1K memory: FED00000 - FED003FF */ + ) + }) + } + /* Real-time clock */ + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0070, 0x0070, 0x10, 0x02) + IRQNoFlags () {8} + IO (Decode16, 0x0072, 0x0072, 0x02, 0x06) + }) + } + + /* Keyboard seems to be important for WinXP install */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Address Range Minimum + 0x0060, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IO (Decode16, + 0x0064, // Address Range Minimum + 0x0064, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IRQNoFlags () + {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () + { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Store (_SB.PCI0.LPC.FDEN, Local0) + If (LEqual (Local0, 0)) + { + Return (0x00) + } + Else + { + Return (0x0F) + } + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + + /* Parallel port */ + Device (LPT) + { + Name (_HID, EisaId ("PNP0400")) + Method (_STA, 0, NotSerialized) + { + Store (_SB.PCI0.LPC.LPEN, Local0) + If (LEqual (Local0, 0)) + { + Return (0x00) + } + Else + { + Return (0x0F) + } + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) + IRQNoFlags () {7} + }) + Return (BUF0) + } + } + + /* Serial Ports */ + Device (COM1) + { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, 0x01) + Method (_STA, 0, NotSerialized) + { + Store (_SB.PCI0.LPC.CAEN, Local0) + If (LEqual (Local0, 0)) + { + Return (0x00) + } + Else + { + Return (0x0F) + } + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08) + IRQNoFlags () {4} + }) + Return (BUF0) + } + } + + Device (COM2) + { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + Store (_SB.PCI0.LPC.CBEN, Local0) + If (LEqual (Local0, 0)) + { + Return (0x00) + } + Else + { + Return (0x0F) + } + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08) + IRQNoFlags () {3} + }) + Return (BUF0) + } + } + } + } + + /* PCI express root port */ +#define pcie_root_port(id, dev, fn) \ + Scope (_SB.PCI0) { \ + Device (PRP##id) { \ + Name (_ADR, 0x##dev##fn) \ + } \ + } + pcie_root_port(0, 4, 0000) + pcie_root_port(1, 18, 0000) + pcie_root_port(2, 18, 0001) + pcie_root_port(3, 18, 0002) + pcie_root_port(4, 18, 0003) + pcie_root_port(5, 18, 0004) + pcie_root_port(6, 18, 0005) + + Scope (_SB.PCI0) { + Device (PRP7) { + Name (_ADR, 0x00190000) + } + } + + /* PCI express upstream port */ +#define pcie_downstream_port(dev) \ + Device (PDP##dev) { \ + Name (_ADR, 0x##dev##0000) \ + } + +#define pcie_upstream_port(fn) \ + Scope (_SB.PCI0.PRP7) { \ + Device (PUP##fn) { \ + Name (_ADR, 0x##0000##fn) \ + pcie_downstream_port(0) \ + pcie_downstream_port(1) \ + pcie_downstream_port(2) \ + pcie_downstream_port(3) \ + pcie_downstream_port(4) \ + pcie_downstream_port(5) \ + pcie_downstream_port(6) \ + pcie_downstream_port(7) \ + pcie_downstream_port(8) \ + pcie_downstream_port(9) \ + pcie_downstream_port(a) \ + pcie_downstream_port(b) \ + pcie_downstream_port(c) \ + pcie_downstream_port(d) \ + pcie_downstream_port(e) \ + pcie_downstream_port(f) \ + } \ + } + pcie_upstream_port(0) + pcie_upstream_port(1) + pcie_upstream_port(2) + pcie_upstream_port(3) + pcie_upstream_port(4) + pcie_upstream_port(5) + pcie_upstream_port(6) + pcie_upstream_port(7) + + + /* PCI to PCI Bridge on bus 0*/ + Scope (_SB.PCI0) { + Device (PCI9) { + Name (_ADR, 0x1e0000) /* 0:1e.00 */ + Name (_UID, 9) + } + } + +#define pci_bridge(id, dev, uid) \ + Scope (_SB.PCI0.PCI9) { \ + Device (PCI##id) { \ + Name (_ADR, 0x##dev##0000) \ + Name (_UID, uid) \ + } \ + } + pci_bridge(0, 1c, 5) + pci_bridge(1, 1d, 6) + pci_bridge(2, 1e, 7) + pci_bridge(3, 1f, 8) + + /* PCI IRQs */ + Scope(_SB) { +#define define_link(link, uid, reg) \ + Device(link){ \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate(){ \ + Interrupt (, Level, ActiveHigh, \ + Shared) \ + { 5, 10, 11 } \ + }) \ + Method (_STA, 0, NotSerialized) \ + { \ + Store (0x0B, Local0) \ + If (And (0x80, reg, Local1)) \ + { \ + Store (0x09, Local0) \ + } \ + Return (Local0) \ + } \ + Method (_DIS, 0, NotSerialized) \ + { \ + Or (reg, 0x80, reg) \ + } \ + Method (_CRS, 0, NotSerialized) \ + { \ + Name (PRR0, ResourceTemplate () \ + { \ + Interrupt (, Level, ActiveHigh, \ + Shared) \ + {1} \ + }) \ + CreateDWordField (PRR0, 0x05, TMP) \ + And (reg, 0x0F, Local0) \ + Store (Local0, TMP) \ + Return (PRR0) \ + } \ + Method (_SRS, 1, NotSerialized) \ + { \ + CreateDWordField (Arg0, 0x05, TMP) \ + Store (TMP, reg) \ + } \ + } + + define_link(LNKA, 0, _SB.PCI0.LPC.PRQA) + define_link(LNKB, 1, _SB.PCI0.LPC.PRQB) + define_link(LNKC, 2, _SB.PCI0.LPC.PRQC) + define_link(LNKD, 3, _SB.PCI0.LPC.PRQD) + define_link(LNKE, 4, _SB.PCI0.LPC.PRQE) + define_link(LNKF, 5, _SB.PCI0.LPC.PRQF) + define_link(LNKG, 6, _SB.PCI0.LPC.PRQG) + define_link(LNKH, 7, _SB.PCI0.LPC.PRQH) + } + + /* CPU hotplug */ + Scope(_SB) { + /* Objects filled in by run-time generated SSDT */ + External(NTFY, MethodObj) + External(CPON, PkgObj) + + /* Methods called by run-time generated SSDT Processor objects */ + Method (CPMA, 1, NotSerialized) { + // _MAT method - create an madt apic buffer + // Local0 = CPON flag for this cpu + Store(DerefOf(Index(CPON, Arg0)), Local0) + // Local1 = Buffer (in madt apic form) to return + Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1) + // Update the processor id, lapic id, and enable/disable status + Store(Arg0, Index(Local1, 2)) + Store(Arg0, Index(Local1, 3)) + Store(Local0, Index(Local1, 4)) + Return (Local1) + } + Method (CPST, 1, NotSerialized) { + // _STA method - return ON status of cpu + // Local0 = CPON flag for this cpu + Store(DerefOf(Index(CPON, Arg0)), Local0) + If (Local0) { Return(0xF) } Else { Return(0x0) } + } + Method (CPEJ, 2, NotSerialized) { + // _EJ0 method - eject callback + Sleep(200) + } + + /* CPU hotplug notify method */ + OperationRegion(PRST, SystemIO, 0xaf00, 32) + Field (PRST, ByteAcc, NoLock, Preserve) + { + PRS, 256 + } + Method(PRSC, 0) { + // Local5 = active cpu bitmap + Store (PRS, Local5) + // Local2 = last read byte from bitmap + Store (Zero, Local2) + // Local0 = cpuid iterator + Store (Zero, Local0) + While (LLess(Local0, SizeOf(CPON))) { + // Local1 = CPON flag for this cpu + Store(DerefOf(Index(CPON, Local0)), Local1) + If (And(Local0, 0x07)) { + // Shift down previously read bitmap byte + ShiftRight(Local2, 1, Local2) + } Else { + // Read next byte from cpu bitmap + Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2) + } + // Local3 = active state for this cpu + Store(And(Local2, 1), Local3) + + If (LNotEqual(Local1, Local3)) { + // State change - update CPON with new state + Store(Local3, Index(CPON, Local0)) + // Do CPU notify + If (LEqual(Local3, 1)) { + NTFY(Local0, 1) + } Else { + NTFY(Local0, 3) + } + } + Increment(Local0) + } + Return(One) + } + } + + Scope (_GPE) + { + Name(_HID, "ACPI0006") + + Method(_L00) { + Return(0x01) + } + Method(_L01) { + // CPU hotplug event + Return(_SB.PRSC()) + } + Method(_L02) { + Return(0x01) + } + Method(_L03) { + Return(0x01) + } + Method(_L04) { + Return(0x01) + } + Method(_L05) { + Return(0x01) + } + Method(_L06) { + Return(0x01) + } + Method(_L07) { + Return(0x01) + } + Method(_L08) { + Return(0x01) + } + Method(_L09) { + Return(0x01) + } + Method(_L0A) { + Return(0x01) + } + Method(_L0B) { + Return(0x01) + } + Method(_L0C) { + Return(0x01) + } + Method(_L0D) { + Return(0x01) + } + Method(_L0E) { + Return(0x01) + } + Method(_L0F) { + Return(0x01) + } + } +}
From: Jason Baron jbaron@redhat.com
Add support for acpi hotplug to q35. Copied from the piix acpi table.
Reviewed-by: Paolo Bonzini pbonzini@redhat.com Signed-off-by: Jason Baron jbaron@redhat.com --- src/q35-acpi-dsdt.dsl | 61 +++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 56 insertions(+), 5 deletions(-)
diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl index 4e16d24..fb62323 100644 --- a/src/q35-acpi-dsdt.dsl +++ b/src/q35-acpi-dsdt.dsl @@ -83,6 +83,21 @@ DefinitionBlock ( Name (_ADR, 0x00) Name (_UID, 1)
+ + OperationRegion(PCST, SystemIO, 0xae00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32, + } + + OperationRegion(SEJ, SystemIO, 0xae08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32, + } + + // _OSC: based on sample of ACPI3.0b spec Name(SUPP,0) // PCI _OSC Support Field value Name(CTRL,0) // PCI _OSC Control Field value @@ -872,6 +887,41 @@ DefinitionBlock ( } }
+/**************************************************************** + * PCI hotplug + ****************************************************************/ + + Scope(_SB.PCI0) { + /* Methods called by bulk generated PCI devices below */ + + /* Methods called by hotplug devices */ + Method (PCEJ, 1, NotSerialized) { + // _EJ0 method - eject callback + Store(ShiftLeft(1, Arg0), B0EJ) + Return (0x0) + } + + /* Hotplug notification method supplied by SSDT */ + External (_SB.PCI0.PCNT, MethodObj) + + /* PCI hotplug notify method */ + Method(PCNF, 0) { + // Local0 = iterator + Store (Zero, Local0) + While (LLess(Local0, 31)) { + Increment(Local0) + If (And(PCIU, ShiftLeft(1, Local0))) { + PCNT(Local0, 1) + } + If (And(PCID, ShiftLeft(1, Local0))) { + PCNT(Local0, 3) + } + } + Return(One) + } + + } + Scope (_GPE) { Name(_HID, "ACPI0006") @@ -879,12 +929,13 @@ DefinitionBlock ( Method(_L00) { Return(0x01) } - Method(_L01) { - // CPU hotplug event - Return(_SB.PRSC()) + Method(_E01) { + // PCI hotplug event + Return(_SB.PCI0.PCNF()) } - Method(_L02) { - Return(0x01) + Method(_E02) { + // CPU hotplug event + Return(_SB.PRSC()) } Method(_L03) { Return(0x01)
From: Jan Kiszka jan.kiszka@siemens.com
Seems important for Windows.
Reviewed-by: Paolo Bonzini pbonzini@redhat.com Signed-off-by: Jan Kiszka jan.kiszka@siemens.com Signed-off-by: Jason Baron jbaron@redhat.com --- src/q35-acpi-dsdt.dsl | 46 +++++++++++++++++++++++++++++++++------------- 1 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl index c9fa5c6..4e16d24 100644 --- a/src/q35-acpi-dsdt.dsl +++ b/src/q35-acpi-dsdt.dsl @@ -161,19 +161,10 @@ DefinitionBlock ( #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \ - Package() { nr##ffff, 0, 0, gsi0 }, \ - Package() { nr##ffff, 1, 0, gsi1 }, \ - Package() { nr##ffff, 2, 0, gsi2 }, \ - Package() { nr##ffff, 3, 0, gsi3 } - -#define GSIA 0x10 -#define GSIB 0x11 -#define GSIC 0x12 -#define GSID 0x13 -#define GSIE 0x14 -#define GSIF 0x15 -#define GSIG 0x16 -#define GSIH 0x17 + Package() { nr##ffff, 0, gsi0, 0 }, \ + Package() { nr##ffff, 1, gsi1, 0 }, \ + Package() { nr##ffff, 2, gsi2, 0 }, \ + Package() { nr##ffff, 3, gsi3, 0 }
#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID) #define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA) @@ -778,6 +769,35 @@ DefinitionBlock ( define_link(LNKF, 5, _SB.PCI0.LPC.PRQF) define_link(LNKG, 6, _SB.PCI0.LPC.PRQG) define_link(LNKH, 7, _SB.PCI0.LPC.PRQH) + +#define define_gsi_link(link, uid, gsi) \ + Device(link){ \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt (, Level, ActiveHigh, \ + Shared) \ + { gsi } \ + }) \ + Method (_CRS, 0, NotSerialized) \ + { \ + Return (ResourceTemplate () { \ + Interrupt (, Level, ActiveHigh, \ + Shared) \ + { gsi } \ + }) \ + } \ + Method (_SRS, 1, NotSerialized) { } \ + } \ + + define_gsi_link(GSIA, 0, 0x10) + define_gsi_link(GSIB, 0, 0x11) + define_gsi_link(GSIC, 0, 0x12) + define_gsi_link(GSID, 0, 0x13) + define_gsi_link(GSIE, 0, 0x14) + define_gsi_link(GSIF, 0, 0x15) + define_gsi_link(GSIG, 0, 0x16) + define_gsi_link(GSIH, 0, 0x17) }
/* CPU hotplug */
On 10/19/12 22:40, Jason Baron wrote:
Hi,
Seabios bits for q35 support, I'm posting the qemu changes separately. The patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the qemu command line. Hopefully, we can make it the default for x86 at some future point when we feel comfortable with it.
Series looks good to me.
cheers, Gerd
-
Gerd Hoffmann -
Jason Baron