[SeaBIOS] [PATCH 1/2] Separate out 16bit PCI-BIOS entry point from regular int 0x1a entry point.

[Kevin O'Connor]

The PCI-BIOS entry point can be called in 16bit protected mode, so
separate its entry code from the legacy 0x1a code.

Signed-off-by: Kevin O'Connor 
---
 src/clock.c     |  1 -
 src/config.h    |  2 +-
 src/pcibios.c   | 16 ++++++++--------
 src/post.c      |  2 +-
 src/romlayout.S | 15 +++++++++++++--
 5 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/src/clock.c b/src/clock.c
index 79b18f9..2ab6adb 100644
--- a/src/clock.c
+++ b/src/clock.c
@@ -552,7 +552,6 @@ handle_1a(struct bregs *regs)
     case 0x05: handle_1a05(regs); break;
     case 0x06: handle_1a06(regs); break;
     case 0x07: handle_1a07(regs); break;
-    case 0xb1: handle_1ab1(regs); break;
     default:   handle_1aXX(regs); break;
     }
 }
diff --git a/src/config.h b/src/config.h
index 0b9b1ab..8b888b9 100644
--- a/src/config.h
+++ b/src/config.h
@@ -94,7 +94,7 @@
 #define DEBUG_ISR_hwpic2 5
 #define DEBUG_HDL_pnp 1
 #define DEBUG_HDL_pmm 1
-#define DEBUG_HDL_pcibios32 9
+#define DEBUG_HDL_pcibios 9
 #define DEBUG_HDL_apm 9

#define DEBUG_unimplemented 2
diff --git a/src/pcibios.c b/src/pcibios.c
index 0f3ec5b..3c5f519 100644
--- a/src/pcibios.c
+++ b/src/pcibios.c
@@ -201,19 +201,19 @@ handle_1ab1(struct bregs *regs)
     }
 }

+// Entry point for pci bios functions.
+void VISIBLE16 VISIBLE32SEG
+handle_pcibios(struct bregs *regs)
+{
+    debug_enter(regs, DEBUG_HDL_pcibios);
+    handle_1ab1(regs);
+}
+

/****************************************************************
  * 32bit interface
  ****************************************************************/

-// Entry point for 32bit pci bios functions.
-void VISIBLE32SEG
-handle_pcibios32(struct bregs *regs)
-{
-    debug_enter(regs, DEBUG_HDL_pcibios32);
-    handle_1ab1(regs);
-}
-
 struct bios32_s {
     u32 signature;
     u32 entry;
diff --git a/src/post.c b/src/post.c
index 4d3262f..ff201fa 100644
--- a/src/post.c
+++ b/src/post.c
@@ -64,7 +64,7 @@ ivt_init(void)
     SET_IVT(0x17, FUNC16(entry_17));
     SET_IVT(0x18, FUNC16(entry_18));
     SET_IVT(0x19, FUNC16(entry_19_official));
-    SET_IVT(0x1a, FUNC16(entry_1a));
+    SET_IVT(0x1a, FUNC16(entry_1a_official));
     SET_IVT(0x40, FUNC16(entry_40));

// INT 60h-66h reserved for user interrupt
diff --git a/src/romlayout.S b/src/romlayout.S
index b1628ef..b152b3e 100644
--- a/src/romlayout.S
+++ b/src/romlayout.S
@@ -334,19 +334,26 @@ entry_apm32:
         popfl
         lretl

-// PCI-BIOS 32bit entry point
+// PCI-BIOS entry points
         DECLFUNC entry_pcibios32
 entry_pcibios32:
         pushfl
         pushl %gs               // Backup %gs and set %gs=%ds
         pushl %ds
         popl %gs
-        ENTRY_ARG_ESP _cfunc32seg_handle_pcibios32
+        ENTRY_ARG_ESP _cfunc32seg_handle_pcibios
         popl %gs
         popfl
         lretl

+        .code16gcc
+        DECLFUNC entry_pcibios16
+entry_pcibios16:
+        ENTRY_ARG handle_pcibios
+        iretw
+
 // BIOS32 support
+        .code32
         DECLFUNC entry_bios32
 entry_bios32:
         pushfl
@@ -600,6 +607,10 @@ entry_10_0x0f:
         // 0xfa6e - vgafont8 in font.c

ORG 0xfe6e
+        .global entry_1a_official
+entry_1a_official:
+        cmpb $0xb1, %ah
+        je entry_pcibios16      // PCIBIOS calls can be in protected mode
         IRQ_ENTRY_ARG 1a

ORG 0xfea5