On Sat, May 31, 2014 at 12:12:13PM +0200, Paolo Bonzini wrote:
Il 31/05/2014 03:20, Kevin O'Connor ha scritto:
Change the multi-processor init code to trampoline into 32bit mode on each of the additional processors. Implement an atomic lock so that each processor performs its initialization serially.
I don't see much benefit in this change, in fact the new code is more complex than the old one...
Thanks for reviewing!
The reason I implemented this is to reduce the amount of 16bit code. The fw/smp.c file is currently being compiled in 16bit mode just to pick up the ~30 lines of assembler. I'd prefer to jump into 32bit mode to avoid that.
As to converting the handler to C code - I agree with you on code complexity, however I do think the existing assembler was already sufficiently complex. Also, being able to use dprintf() is quite nice.
But anyway, if you prefer to go this way I have just a couple observations on the patch:
- acquiring the lock can be done simply by a "1: lock btsl; jc 1b"; no need
to use the cmpxchg.
Thanks - that is an improvement.
- There's no need to acquire the lock repeatedly in the BSP, I think
writing the loop in assembly is acceptable:
I'll rework the patch and take a look at that.