On Mon, Aug 23, 2010 at 12:33:24AM +0200, Carl-Daniel Hailfinger wrote:
On 22.08.2010 19:02, Kevin O'Connor wrote:
I'm not sure what you mean by "4G-2M" - are you suggesting running XIP in the "flash" chip? This is possible in qemu/kvm, but it's not something you'd want to do on real hardware. Accesses to the flash chip are terribly slow - on real hardware you want to copy the code from flash to ram as soon as possible.
If you can switch on caching for the flash area and do it correctly, why would it be slow during POST? Of course you have to switch off caching of flash once you pass control to the bootloader, and then flash will be slow, but for initial POST it should work fine.
(You typically want to compress everything in flash also.)
Of course that's indeed a compelling argument.
Caching flash would mitigate some of the slowness, but as you point out, it has complexities and is still not really a great solution. It's far simpler and more robust to copy the code to ram on real hardware. (In contrast, on qemu/kvm it's really quite simple to just jump into the extra copy of SeaBIOS at 0xfffe0000.)