On Tue, Sep 29, 2015 at 10:19:19PM +0200, Rudolf Marek wrote:
- The reason why PAE is interesting (instead of standard i386 paging) is that it allows for 64bit mappings and because one can set it up with just a single level page directory of 2MB pages. The single level page directory makes maintaining it much easier.
There is a performance penalty if you do it for first 2MB of phys memory on some P6/XeonP4 CPUs. Others could trigger undefined behaviour.
The reason for this are the special regions in the 640KB-1MB covered by various MTRRs. See 11.11.9 Large Page Size Considerations in the Intel manual for the details.
Thanks - good catch. It looks like that would require using 4KB pages for identity mapping the first 2MB or ram.