Hello Daniel,

 

No, unfortunately this cannot be changed. So there is no possibility to map the 32 bit BAR in a higher memory region (where the 64 bit BAR’s are located)?

 

Kind regards,


Wannes

 

From: Daniel Paziyski <danielpaziyski@gmail.com>
Sent: Wednesday, April 12, 2023 9:19 AM
To: Wannes Bouwen (Nokia) <wannes.bouwen@nokia.com>; seabios@seabios.org
Subject: Re: [SeaBIOS] Large 32 bit BAR's

 

 

 

CAUTION: This is an external email. Please be very careful when clicking links or opening attachments. See the URL nok.it/ext for additional information.

 

Hello,

 

For a device with such a big 32 bit BAR, it would be a challenge to fit it inside the 32 bit window, since the RAM region available on <4GB must be specially tuned with help from the emulator (which, as far as I am aware, isn't available) to give space for BAR allocations there. Is there a possibility for that emulated PCIe device to be configured to expose a 64 bit BAR instead?

 

Regards,

Daniel

 

On 4/12/23 08:23, Wannes Bouwen (Nokia) wrote:

Hello,

 

I’m running a x86 QEMU with Ubuntu. On this system we want to emulate a PCIe device which contains a large 32-bit BAR (2 GiB). This is not working and I get following error:

SeaBIOS (version rel-1.14.0-0-g155821a-20210629_105355-sharpie)

BUILD: gcc: (GCC) 4.8.5 20150623 (Red Hat 4.8.5-36) binutils: version 2.27-34.base.el7

No Xen hypervisor found.

Running on QEMU (q35)

Running on KVM

Found QEMU fw_cfg

QEMU fw_cfg DMA interface supported

qemu/e820: addr 0x0000000000000000 len 0x0000000080000000 [RAM]

qemu/e820: addr 0x0000000100000000 len 0x0000000180000000 [RAM]

Relocating init from 0x000d4de0 to 0x7ffa9420 (size 93008)

Moving pm_base to 0x600

kvmclock: at 0xeb040 (msr 0x4b564d01)

kvmclock: stable tsc, 2992 MHz

CPU Mhz=2992 (kvmclock)

=== PCI bus & bridge init ===

PCI: pci_bios_init_bus_rec bus = 0x0

PCI: pci_bios_init_bus_rec bdf = 0x20

PCI: primary bus = 0x0

PCI: secondary bus = 0xff -> 0x1

PCI: pci_bios_init_bus_rec bus = 0x1

PCI: subordinate bus = 0x0 -> 0x1

=== PCI device probing ===

Found 12 PCI devices (max PCI bus is 01)

PCIe: using q35 mmconfig at 0xb0000000

=== PCI new allocation pass #1 ===

PCI: check devices

PCI: secondary bus 1 size 00000000 type io

PCI: secondary bus 1 size 100000000 type mem

PCI: secondary bus 1 size 100000000 type prefmem

=== PCI new allocation pass #2 ===

PCI: IO: c000 - c0ff

PCI: 32: 00000000c0000000 - 00000000fec00000

PCI: out of 32bit address space

 

I’ve had a look at the code and it seems that 32-bit BAR’s have a limited memory region available (less than 1 GiB). Is there a possibility to use such large 32-bit BAR’s in combination with SeaBios by e.g. mapping them in the higher memory region where 64-bit BAR’s are mapped?

 

Thanks in advance!

 

Kind regards,


Wannes



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