Add a piix4 memory setup function to make the control flow more clear.
Set the new mtrr_base variable (added by q35 patch set) to the start of the 32bit pci window to make sure the mtrr entry added covers the I/O window.
Make the 32bit pci window start at 0x80000000, 0xc0000000 or 0xe000000 (depending on the memory installed) so we can cover the whole window with a single mtrr entry.
Signed-off-by: Gerd Hoffmann kraxel@redhat.com --- src/pciinit.c | 18 +++++++++++++++--- 1 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/pciinit.c b/src/pciinit.c index 93a53e8..28c77ed 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -660,6 +660,18 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) } }
+void i440fx_mem_addr_init(struct pci_device *dev, void *arg) +{ + u64 *start = (u64 *)arg; + + if (RamSize <= 0x80000000) + *start = 0x80000000; + else if (RamSize <= 0xc0000000) + *start = 0xc0000000; + + mtrr_base = *start; +} + void mch_mem_addr_init(struct pci_device *dev, void *arg) { u64 *start = (u64 *)arg; @@ -670,6 +682,8 @@ void mch_mem_addr_init(struct pci_device *dev, void *arg) }
static const struct pci_device_id pci_mem_addr_tbl[] = { + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, + i440fx_mem_addr_init), PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH, mch_mem_addr_init), PCI_DEVICE_END, @@ -677,9 +691,7 @@ static const struct pci_device_id pci_mem_addr_tbl[] = {
static void pci_bios_map_devices(struct pci_bus *busses) { - pcimem_start = RamSize; - - /* let's add in mmconfig space on q35 */ + /* chipset specific memory setup */ pci_find_init_device(pci_mem_addr_tbl, &pcimem_start);
if (pci_bios_init_root_regions(busses)) {