I have been having trouble getting PII to work with memory from powerup. I just now realized that I'm seeing basically the same problem on the Intel and SiS motherboards. Engineers at SiS, using the same linuxbios romimage as I am using, has no troubles on the motherboard BUT: they are using Celeron. (see the linuxbios web page: I can still get the intel motherboard up with linuxbios, but I have to let the flash recovery code run first by twiddling the jumper).
The symptom is that during memory init, at some point the processor seems to take a trap during a memory write. It is as though some piece of hardware between the processor and memory is unhappy :-)
I'm working with SiS to try a different motherboard. But: I'm now wondering if I'm encountering some kind of PII L2 Cache init problem on the Slot 1 cards I'm using here. I'm very suspicious that I'm seeing a particular kind of problem on my Slot 1 PII systems that SiS is not seeing using a Celeron, and that I'm seeing the same kind of problem on both Intel and SiS mainboards.
Any comments on this? Any thoughts? Anyone know if anything special happens for L2 cache on a Slot 1 card at powerup? It would probably look like an IN or OUT to an undocumented address (undocumented since this is Intel we're talking about here).
ron p.s. linuxbios: http://www.acl.lanl.gov/linuxbios
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|<><><><><> Original message from Ronald G Minnich <><><><><> |I have been having trouble getting PII to work with memory from powerup. I |just now realized that I'm seeing basically the same problem on the Intel |and SiS motherboards. Engineers at SiS, using the same linuxbios romimage |as I am using, has no troubles on the motherboard BUT: they are using |Celeron. (see the linuxbios web page: I can still get the intel |motherboard up with linuxbios, but I have to let the flash recovery code |run first by twiddling the jumper). | |The symptom is that during memory init, at some point the processor seems |to take a trap during a memory write. It is as though some piece of |hardware between the processor and memory is unhappy :-) | |I'm working with SiS to try a different motherboard. But: I'm now |wondering if I'm encountering some kind of PII L2 Cache init problem on |the Slot 1 cards I'm using here. I'm very suspicious that I'm seeing a |particular kind of problem on my Slot 1 PII systems that SiS is not seeing |using a Celeron, and that I'm seeing the same kind of problem on both |Intel and SiS mainboards. | |Any comments on this? Any thoughts? Anyone know if anything special |happens for L2 cache on a Slot 1 card at powerup? It would probably look |like an IN or OUT to an undocumented address (undocumented since this is |Intel we're talking about here). | |ron |p.s. linuxbios: http://www.acl.lanl.gov/linuxbios
Ron, in going through the SuperMicro P6DGE BIOS they definitely write a number of reserved bits and in the 440GX chip. It is hard to know exactly what needs to be done to get the board to talk to memory. What we have observed is that the processor doesn't trap, but that it doesn't read back from memory what was written. After we think we have memory turned on we do a
push %eax pop %ebx cmp %eax,%ebx 1: bne 1b
The PII then spins. I've yet to find anyone at Intel that will give me the time of day. SuperMicro was initially helpful but they have returned my most recent calls.
TJ Merritt tjm@codegen.com 1-415-834-9111 - To unsubscribe: send mail to majordomo@freiburg.linux.de with 'unsubscribe openbios' in the body of the message
On Wed, 24 May 2000, Thomas J. Merritt wrote:
Ron, in going through the SuperMicro P6DGE BIOS they definitely write a number of reserved bits and in the 440GX chip. It is hard to know exactly what needs to be done to get the board to talk to memory. What we have observed is that the processor doesn't trap, but that it doesn't read back from memory what was written. After we think we have memory turned on we do a
Why don't you send me what you've done on yours, and look at what I've done on mine. I have experienced the "can't read what you write" syndrome and have dealt with it a number of times -- many times in my case it was the result of a bad Mode Register Set.
Thanks
ron
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Ronald G Minnich wrote:
I have been having trouble getting PII to work with memory from powerup. I just now realized that I'm seeing basically the same problem on the Intel and SiS motherboards. Engineers at SiS, using the same linuxbios romimage as I am using, has no troubles on the motherboard BUT: they are using Celeron. (see the linuxbios web page: I can still get the intel motherboard up with linuxbios, but I have to let the flash recovery code run first by twiddling the jumper).
Sorry, Ron, but you probably got some misunderstanding of the situation here SiS. We are using PII processors as you (??) but the M/B are different. The M/B send to you was made by some infamous OEM, an the M/B tested here was what the real "demo board" made in-house.
The symptom is that during memory init, at some point the processor seems to take a trap during a memory write. It is as though some piece of hardware between the processor and memory is unhappy :-)
I'm working with SiS to try a different motherboard. But: I'm now wondering if I'm encountering some kind of PII L2 Cache init problem on the Slot 1 cards I'm using here. I'm very suspicious that I'm seeing a particular kind of problem on my Slot 1 PII systems that SiS is not seeing using a Celeron, and that I'm seeing the same kind of problem on both Intel and SiS mainboards.
Any comments on this? Any thoughts? Anyone know if anything special happens for L2 cache on a Slot 1 card at powerup? It would probably look like an IN or OUT to an undocumented address (undocumented since this is Intel we're talking about here).
We can reach some point in intel_main.c on our M/B with all DRAM correctly sized/detected, so it probably not an undocumented CPU thing but an undocumentd, screw-up M/B thing.
Anyway, we will send you the M/B with DIMM we are testing to you, of course, the flash rom and the romimage "pre-installed" too.
After that we will purchase TWO identical M/B made by LeadTek (WinFast 6300MA), DIMM, flash rom, one for each of us. The M/B is only avaliable in Socket 370, so we are asking you if it is O.K.
Ollie - To unsubscribe: send mail to majordomo@freiburg.linux.de with 'unsubscribe openbios' in the body of the message
On Thu, 25 May 2000, Ollie Lho wrote:
Sorry, Ron, but you probably got some misunderstanding of the situation here SiS. We are using PII processors as you (??) but the M/B are different. The M/B send to you was made by some infamous OEM, an the M/B tested here was what the real "demo board" made in-house.
Oh, sorry, my fault.
We can reach some point in intel_main.c on our M/B with all DRAM correctly sized/detected, so it probably not an undocumented CPU thing but an undocumentd, screw-up M/B thing.
That is certainly the preferred case, since I don't want to reverse engineer the PII :-)
Sorry for my confusion!
ron
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I'm cleaning out my mailbox. You saw I got the L440GX+ mainboard going right?
ron
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Ollie Lho -
Ronald G Minnich -
Thomas J. Merritt