Parallel Port EPROM simulator

[Qiwei Xiao]

Parallel Port EPROM Simulator

Copyright 1998, Qiwei Xiao ([e-mail]), All Right Reserved

Free for noncommercial use. Absolutely no warranty of any kind.

Note: IC1, IC2 and IC3 (74ACT541) can be replaced by two 74ACT841 to
save one IC.

For a PC parallel port, the control output (base+2) has 4 lines:
C0-C3. They are open collector so you might need a pull-up resistor
for each of them. C5 controls the state of bi-directional data
port: if C5=0, the port acts as an ordinary output port; if
C5=1, the output port is in high impedance state (and effectively
becomes an input port) so any outside source can drive the bus and 
can be read in. A good PC parallel port tutorial is in 
http://www.rmii.com/~hisys/parport.html.

How it works:

C5=1, C1,C2,C3 = 000: Normal Mode
The simulator acts like an ordinary ROM. The extra ICs on the bus 
add about 5ns delay which shouldn't be a problem for FLASH chips 
whose delay is typical in the 70-100ns range.

C1,C2,C3 != 000: Programming Mode (C1,C2,C3 "park" on 111)
Read operation: 
  (1) Set C0=1, then C5=0. Order is important.
  (2) Place address byte 1 on the data port, send a pulse to 
      IC7 to latch it. (i.e., C1,C2,C3 = 111 -> 011 -> 111) 
  (3) Place address byte 2 on the data port, send a pulse to 
      IC6 to latch it.
  (4) Place address byte 3 on the data port, send a pulse to
      IC5 to latch it. 
  (5) Set C5=1, then C0=0. Order is important.
  (6) Read in data.

Repeat the steps so all the data are read in. High address byte
   needs to be changed once for every 256 low address byte changes.

Write operation:
   Same as read operation, the only difference is in step (5): 
   (5) set C5=0, send out the byte to be written on the data port, and 
       send a pulse to the "Write Enable (WE)" line of IC9.