Interesting, can you tell more about this project? Did you also modify QEMU to emulate the HW setup?
The project is currently in stealth mode, so I can't give any details for now.
We should try to isolate the dependencies for QEMU, even if QEMU is probably the most interesting use case for OpenBIOS these days. Could you tell more about those bugs and even better, publish your changes?
A few issues :
- arch/sparc32/wuf.S : WIM register updates must not be immediately followed by instructions depending on WIM value (SparcV8, §B.29, page 133) : wr %twin_tmp1, 0x0, %wim /* Make window 'I' invalid */ + nop + nop + nop restore %g0, %g0, %g0 /* Restore to window 'O' */
- arc/sparc32/entry.S : The FP (frame ptr) register is never initialised. Registers are not initialized after a RESET (SparcV8, page 75).
- arch/sparc32/entry.S : MMU activation is written as : set highmem, %g2 set 1, %g1 jmp %g2 sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu
It doesn't work because there is no precise synchronisation between MMU registers updates and instruction fetches (because of pipelining) MMU activation must be done in a area where virtual and physical adresses are equal ( VA=FF00_0000 --> PA=F_FF00_0000 ). The intial page table is modified to add this mapping and the activation sequence is : - jump from 0_ to F_something (PROM boot mode) - activate the MMU - plenty of NOPs - jump to "highmem" I also eventually disassembled Sun ROMs, and found sequences like that : sta %l1,[%l0],4 iflush nop nop nop nop nop
I can post patches, but they won't change anything to QEMU (at best). The currently used version of OpenBIOS isn't the latest (SVN 1046), I may need to do some cleanup.
(...and sorry for the previous message's bad formatting)