[OpenBIOS] get ints turned on

[Wallace I. Kroeker]

Hello,

At least part of the puzzle is getting the PIIX set up.

On my system (a 440bx) there is a PIIX4 (sometimes called the SouthBridge I
believe) this contains the interrupt handler (it used to be a separate
chip(s) on the old systems).

In the OpenBIOS code I set mine up in the SuperIO (I generated one for the
440bx) by writing the values out.
Code follows:
#include <io.h>
#include <types.h>

#define CS440BX_INDEX 0xf2
#define CS440BX_DATA  0xf3

/* Write val to reg# reg. */
#define WRITE_440BX(reg, val) { \
   outb_p(reg, CS440BX_INDEX); \
   outb_p(val, CS440BX_DATA); }

static struct {
   u8 reg;
   u8 val;
}sio_regs[] = {
  { 0x20, 0x11 },     /* ICW1 1st 82C59 setup */
  { 0x21, 0x08 },     /* ICW2 1st 82C59 setup */
  { 0x21, 0x04 },     /* ICW3 1st 82C59 setup */
  { 0x21, 0x01 },     /* ICW4 1st 82C59 setup */
  { 0xA0, 0x11 },     /* ICW1 2nd 82C59 setup */
  /** Linux put out 0x70 for ICW2 ??? why ??? **/
  { 0xA1, 0x08 },     /* ICW2 2nd 82C59 setup */
  { 0xA1, 0x02 },     /* ICW3 2nd 82C59 setup */
  { 0xA1, 0x01 },     /* ICW4 2nd 82C59 setup */
  { 0xff, 0x00 }
};

void sio_init(void)
{
   int i;
   for (i=0; sio_regs[i].reg != 0xff; i++) { 
      WRITE_440BX(sio_regs[i].reg, sio_regs[i].val);
   }
}

The documentation states that you need to program them in order from  ICW1,
ICW2, ICW3, ICW4 for address 0x20 and 0x21 and
ICW1, ICW2, ICW3, ICW4 for 0xA0 and 0xA1

Linux also sets up the interrupts on boot (look for the code near code just
before "steenking BIOS" in setup.S)  This is where he is setting up the
interrupt chips as he would like them.

Now in both the OpenBIOS and Linux the need to set up the IDT to properly
use the interrupt vectors.  The OpenBIOS is probably a littler simpler to
understand:

The OpenBIOS sets up RAMSTART as 0x400

The GDT start at RAMSTART of 0x400 ( note this is mulitply defined in the
assembler code and in the header segment.h ... bad form and error prone)

The GDT is 0x800 bytes big

The IDT starts next at 0xC00.

There is some preliminary set up of these in the boot/boot16/start.asm code

The code in firmware/init/traps.c does further initializing of the interrupt
vector table and viola you get the OpenBIOS firmware responding to
interrupts.  I have added support for Int 0x13 (floppy read write) in so far
as I can issue an int 0x13 as inline assembler in the main.c which cause my
interrupt handler to be called.    (I gave up on writing the floppy driver
as there seems to be some problems getting the floppy to respond properly
and it wasn't critical to what I was doing. )

I have spent my time writing a utility for downloading a real OS via the
serial port instead and am in the process of getting linux bmvlinux to boot.
After I have loaded it into upper memory and vectored to the entry point.  I
am currently looking into the setup.S code to determine how I should be
setting things up to make linux happy.  I believe that I still need to do a
some preliminary IDT setup (as would come with a regular BIOS) so that Linux
can pull it's socks up.  (If I put a simple assembly instruction in upper
memory and call it, it will return.  If I put Linux up there and call it it
currently dies.)

Another thing that Linux folks should watch out for is that Linux can be
compiled to either use BIOS32 (PCI bioses) or do all the PCI enumeration and
setup.  You should compile your kernel to do it's own PCI enumeration.

I have been working on the memory setup and haven't had too much luck yet.
(Ron's 440gx code doesn't work for my system even with minor changes for
chipset differences etc.)

Wallace
> -----Original Message-----
> From:	Ronald G. Minnich [SMTP:[e-mail]]
> Sent:	Thursday, March 16, 2000 9:39 PM
> To:	[e-mail]
> Subject:	Re: [OpenBIOS] Re: Status
>
> On Thu, 16 Mar 2000, Edwin Rhodes wrote:
> > i know this may sound real stupid, but have you checked out Ralf Brown's
> > Interrupt List?
>
> Hmm, tell me more. I think I have, but I'm not sure that Ralf tells you
> how to init the cold hardware to enable timer interrupts.
>
> ron
>
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