OpenBIOS

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4289 discussions

Adding new device in the middle of device-tree
by BALATON Zoltan 17 Jul '17

17 Jul '17

Hello, Is there a way to add a new device in the middle of the device tree (before or after an existing node) from Forth? If I try: dev / new-device " newdev" device-name finish-device show-devs /newdev appears at the end of the device-tree but that's not what I want. I need this device to go at a specific place in the middle but I could not find out how to achieve that. Any ideas? Thank you, BALATON Zoltan

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[PATCH 0/2] SPARC64: complete switch to Simba PCI bridge configuration
by Mark Cave-Ayland 16 Jul '17

16 Jul '17

This is the final set of changes required to switch SPARC64 over to use the QEMU machine configuration with Simba bridges. Note that this is currently pending approval of pre-requisite patches for the corresponding sun4u patchset. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (2): SPARC64: switch to simba PCI bridge machine configuration pci: set cmd646 name and device_type properties to "ide" arch/sparc64/openbios.c | 2 +- drivers/pci.c | 22 ++++++++++++++-------- drivers/pci_database.c | 2 +- 3 files changed, 16 insertions(+), 10 deletions(-) -- 1.7.10.4

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[PATCH 00/13] SPARC64: sabre/simba bridge fixups
by Mark Cave-Ayland 12 Jul '17

12 Jul '17

This patchset prepares the way for changing the QEMU sun4u machine to be much closer to a real Ultra 5. The main change we are aiming for is to replicate the PCI bus topology so that onboard devices are attached behind simba A and simba B is an empty PCI bus (although devices can be added via QEMU's -device syntax). Note that this patch does all of the preparation work but doesn't actually implement the changes required by the switch. This is because the QEMU patches are still awaiting upstream approval and change to the sun4u machine must be synchronised between QEMU and OpenBIOS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (13): SPARC64: increase size of PCI memory space SPARC64: increase size of PCI IO space SPARC64: fix PCI memory base in host ranges SPARC64: fix PCI configuration space size SPARC64: implement custom PCI bus scan for sabre SPARC64: add custom sabre reg property to sabre_config_cb() pci: implement simba_config_cb() for programming device ranges pci: update interrupt-map-mask to include the bus during interrupt comparisons pci: don't set interrupt-map and interrupt-map-mask properties if empty pci: rename SUN4U_INTERRUPT to SUN4U_PCIAINTERRUPT pci: alter ob_configure_pci_device() to return its device phandle pci: use ob_pci_bus_set_interrupt_map() to configure interrupts for Simba PCI bus B pci: map Simba PCI bus A on-board devices to fixed interrupts arch/sparc64/openbios.c | 12 ++-- drivers/pci.c | 175 ++++++++++++++++++++++++++++++++++++++++++----- drivers/pci_database.c | 2 +- drivers/pci_database.h | 1 + 4 files changed, 167 insertions(+), 23 deletions(-) -- 1.7.10.4

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[PATCH 0/5] pci: allow customisation of PCI host bridge ranges
by Mark Cave-Ayland 12 Jul '17

12 Jul '17

Whilst debugging some SPARC64 issues relating to PCI bridges, it became apparent that the logic for generating the ranges property for the PCI host bridge isn't flexible enough to allow generation of the correct values across all architectures. In order to allow per-architecture customisation of PCI host bridge properties, split them out into a separate struct within pci_arch_t and migrate all PCI architectures over to use them. As a side effect we can now remove the rbase and rlen members from pci_arch_t since they are no longer required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (5): pci: define pci_range_t typedef and add it to pci_arch_t struct pci: move memory type enum from drivers/pci.c to include/drivers/pci.h arch: update pci_host_t host_ranges with values for each architecture pci: update pci_set_host_ranges() to use the new pci_arch_t host_ranges arch: remove rbase and rlen from pci_arch_t for all PCI architectures arch/ppc/qemu/init.c | 29 +++++++++++++++++------- arch/sparc64/openbios.c | 6 +++++ arch/x86/openbios.c | 4 ++++ drivers/pci.c | 56 ++++++++++++++--------------------------------- include/drivers/pci.h | 19 ++++++++++++++-- 5 files changed, 64 insertions(+), 50 deletions(-) -- 1.7.10.4

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[PATCH 0/2] pc_kbd: implement 8042 controller and separate keyboard/mouse devices
by Mark Cave-Ayland 12 Jul '17

12 Jul '17

Compared with real SPARC/PReP device trees, an 8042 controller should be modelled as a separate device with keyboard (and optionally mouse) devices beneath it. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (2): pc_kbd: place keyboard device under 8042 controller device pc_kbd: add optional mouse device support for 8042 devices drivers/pc_kbd.c | 112 ++++++++++++++++++++++++++++++++++++++------- drivers/pci.c | 4 +- include/drivers/drivers.h | 4 +- 3 files changed, 100 insertions(+), 20 deletions(-) -- 1.7.10.4

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[PATCH 0/3] Misc fixup patches
by Mark Cave-Ayland 12 Jul '17

12 Jul '17

This is a small set of fixes that came out of my current queue of SPARC64 patches. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (3): vga.fs: do not attempt to map MMIO registers more than once pci: always use devfn 0 for PCI host bridge ranges SPARC64: fix up PCI-EBus interrupt map and ino for PS/2 keyboard device drivers/pci.c | 21 +++++++++++++++------ drivers/vga.fs | 4 +++- 2 files changed, 18 insertions(+), 7 deletions(-) -- 1.7.10.4

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[PATCH] pci: fix accidental io_base reset for PCI host bridge
by Mark Cave-Ayland 12 Jul '17

12 Jul '17

Commit c80a58b added a workaround to allow ioport access through the first PCI bridge found until its base and limits were programmed, so that on-board devices not directly attached to the PCI host bus could be used during OpenBIOS initialisation. Unfortunately the logic was broken, and in fact the reset should only occur if we're the first PCI bridge that isn't the host bridge - otherwise we end up resetting io_base for the PCI host bus causing its devices to be mapped over existing in-built ioports causing strange behaviour. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> --- drivers/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci.c b/drivers/pci.c index db92683..92938a4 100644 --- a/drivers/pci.c +++ b/drivers/pci.c @@ -1426,7 +1426,7 @@ static void ob_configure_pci_bridge(pci_addr addr, /* Always expose the legacy ioports on the first PCI bridge. If we must have legacy devices behind a PCI bridge then they must be on the first one discovered to ensure that the ioports will work. */ - if (*io_base < 0x1000) { + if (primary_bus > 0 && *io_base < 0x1000) { *io_base = 0x0; } -- 1.7.10.4

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[PATCH] vga.fs: add support for QEMU PCI MMIO register access
by Mark Cave-Ayland 18 Jun '17

18 Jun '17

Currently the driver works by using the legacy VGA ioports for programming the display. However this makes it much harder to configure e.g. multiple displays or VGA devices behind multiple PCI bridges. If building for QEMU, default to using the QEMU PCI MMIO registers to program the display. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> --- drivers/vga.fs | 85 ++++++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 68 insertions(+), 17 deletions(-) diff --git a/drivers/vga.fs b/drivers/vga.fs index cbfa46c..d39b062 100644 --- a/drivers/vga.fs +++ b/drivers/vga.fs @@ -47,6 +47,22 @@ fcode-version3 : ioc! ioc!-xt execute ; : iow! iow!-xt execute ; +" le-w!" (find-xt) value le-w!-xt + +: le-w! le-w!-xt execute ; + +\ +\ PCI +\ + +" pci-bar>pci-addr" (find-xt) value pci-bar>pci-addr-xt +: pci-bar>pci-addr pci-bar>pci-addr-xt execute ; + +h# 10 constant cfg-bar0 \ Framebuffer BAR +h# 18 constant cfg-bar2 \ QEMU MMIO ioport BAR +-1 value fb-addr +-1 value mmio-addr + \ \ VGA registers \ @@ -55,12 +71,22 @@ h# 3c0 constant vga-addr h# 3c8 constant dac-write-addr h# 3c9 constant dac-data-addr +defer vga-ioc! + +: vga-legacy-ioc! ( val addr ) + ioc! +; + +: vga-mmio-ioc! ( val addr ) + h# 3c0 - h# 400 + mmio-addr + c! +; + : vga-color! ( r g b index -- ) \ Set the VGA colour registers - dac-write-addr ioc! rot - 2 >> dac-data-addr ioc! swap - 2 >> dac-data-addr ioc! - 2 >> dac-data-addr ioc! + dac-write-addr vga-ioc! rot + 2 >> dac-data-addr vga-ioc! swap + 2 >> dac-data-addr vga-ioc! + 2 >> dac-data-addr vga-ioc! ; \ @@ -86,17 +112,23 @@ h# 1 constant VBE_DISPI_ENABLED \ Bochs VBE register writes \ -: vbe-iow! ( val addr -- ) +defer vbe-iow! + +: vbe-legacy-iow! ( val addr -- ) h# 1ce iow! h# 1d0 iow! ; +: vbe-mmio-iow! ( val addr -- ) + 1 lshift h# 500 + mmio-addr + cr .s cr le-w! +; + \ \ Initialise Bochs VBE mode \ : vbe-init ( -- ) - h# 0 vga-addr ioc! \ Enable blanking + h# 0 vga-addr vga-ioc! \ Enable blanking VBE_DISPI_DISABLED VBE_DISPI_INDEX_ENABLE vbe-iow! h# 0 VBE_DISPI_INDEX_X_OFFSET vbe-iow! h# 0 VBE_DISPI_INDEX_Y_OFFSET vbe-iow! @@ -104,20 +136,14 @@ h# 1 constant VBE_DISPI_ENABLED openbios-video-height VBE_DISPI_INDEX_YRES vbe-iow! depth-bits VBE_DISPI_INDEX_BPP vbe-iow! VBE_DISPI_ENABLED VBE_DISPI_INDEX_ENABLE vbe-iow! - h# 0 vga-addr ioc! - h# 20 vga-addr ioc! \ Disable blanking + h# 0 vga-addr vga-ioc! + h# 20 vga-addr vga-ioc! \ Disable blanking ; \ -\ PCI +\ PCI BAR mapping \ -" pci-bar>pci-addr" (find-xt) value pci-bar>pci-addr-xt -: pci-bar>pci-addr pci-bar>pci-addr-xt execute ; - -h# 10 constant cfg-bar0 \ Framebuffer BAR --1 value fb-addr - : map-fb ( -- ) cfg-bar0 pci-bar>pci-addr if \ ( pci-addr.lo pci-addr.mid pci-addr.hi size ) " pci-map-in" $call-parent @@ -125,6 +151,32 @@ h# 10 constant cfg-bar0 \ Framebuffer BAR then ; +: map-mmio ( -- ) + cfg-bar2 pci-bar>pci-addr if \ ( pci-addr.lo pci-addr.mid pci-addr.hi size ) + " pci-map-in" $call-parent + to mmio-addr + then +; + +\ +\ Legacy IO port or QEMU MMIO accesses +\ +\ legacy: use standard VGA ioport registers +\ MMIO: use QEMU PCI MMIO VGA registers +\ +\ If building for QEMU, default to MMIO access since it allows +\ programming of the VGA card regardless of its position in the +\ PCI topology +\ + +[IFDEF] CONFIG_QEMU +['] vga-mmio-ioc! to vga-ioc! +['] vbe-mmio-iow! to vbe-iow! +[ELSE] +['] vga-legacy-ioc! to vga-ioc! +['] vbe-legacy-iow! to vbe-iow! +[THEN] + \ \ Publically visible words \ @@ -181,6 +233,7 @@ headerless \ : qemu-vga-driver-install ( -- ) + map-mmio vbe-init fb-addr -1 = if map-fb fb-addr to frame-buffer-adr default-font set-font @@ -193,8 +246,6 @@ headerless ; : qemu-vga-driver-init - - vbe-init openbios-video-width encode-int " width" property openbios-video-height encode-int " height" property depth-bits encode-int " depth" property -- 1.7.10.4

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[PATCH 0/8] pci: fix up PCI bridges
by Mark Cave-Ayland 18 Jun '17

18 Jun '17

In order to progress further with sun4u in QEMU, it has become necessary to introduce PCI bridges similar to a real Ultra 5. This is because several OSs make assumptions about the PCI topology, and without the PCI bridge in place will either crash or fail to map memory regions correctly. This first patchset fixes up PCI bridges so that we can now enumerate them correctly. As an idea as to where I'm going with this, if you also take the WIP QEMU branch at https://github.com/mcayland/qemu/tree/sparc64-pcibridge then the output of show-devs looks like this: Welcome to OpenBIOS v1.1 built on Jun 11 2017 06:57 Type 'help' for detailed information 0 > show-devs ffe1bf40 / ffe1c118 /aliases ffe1c240 /openprom (BootROM) ffe26b58 /openprom/client-services ffe1c4f8 /options ffe1c5d8 /chosen ffe1c718 /builtin ffe1c840 /builtin/console ffe26620 /packages ffe28648 /packages/cmdline ffe28898 /packages/disk-label ffe2c8e0 /packages/deblocker ffe2cef8 /packages/grubfs-files ffe2d308 /packages/sun-parts ffe2d720 /packages/elf-loader ffe2b218 /memory@0,0 (memory) ffe2b378 /virtual-memory ffe2d880 /pci@1fe,0 (pci) ffe2e1b0 /pci@1fe,0/pci@1 (pci) ffe2e8c8 /pci@1fe,0/pci@1,1 (pci) ffe2efb0 /pci@1fe,0/pci@1,1/ebus@1 ffe2f7f0 /pci@1fe,0/pci@1,1/ebus@1/eeprom@0 ffe2f968 /pci@1fe,0/pci@1,1/ebus@1/fdthree@0 (block) ffe2feb8 /pci@1fe,0/pci@1,1/ebus@1/su@0 (serial) ffe30248 /pci@1fe,0/pci@1,1/ebus@1/kb_ps2@0 (serial) ffe305b8 /pci@1fe,0/pci@1,1/QEMU,VGA@2 (display) ffe31c30 /pci@1fe,0/pci@1,1/pci-ata@3 (pci-ide) ffe32188 /pci@1fe,0/pci@1,1/pci-ata@3/ide0@4000 (ide) ffe32468 /pci@1fe,0/pci@1,1/pci-ata@3/ide1@4100 (ide) ffe32700 /pci@1fe,0/pci@1,1/pci-ata@3/ide1@4100/cdrom@0 (block) ffe32d88 /pci@1fe,0/NE2000@2 (network) ffe33490 /SUNW,UltraSPARC-IIi (cpu) ok Note I have several more SPARC64-related fixes queued, however as this patchset is starting to get quite unwieldy it makes sense to split this part off separately. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (8): pci: add temporary bus-range property to PCI bridge devices pci: include PCI bus id in ob_pci_decode_unit() pci: create new ob_pci_bridge_node based upon ob_pci_bus_node pci: rename ob_pci_map_in() to ob_pci_bus_map_in() pci: implement ob_pci_bridge_map_in() for PCI-PCI bridge nodes pci: configure base and limit registers during PCI bridge configuration pci: split PCI bus interrupt maps from PCI host bridge interrupt maps pci: allow ob_pci_bus_set_interrupt_map() to take a callback function drivers/pci.c | 186 ++++++++++++++++++++++++++++++++++++++++++++------------- drivers/pci.h | 5 ++ 2 files changed, 150 insertions(+), 41 deletions(-) -- 1.7.10.4

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[PATCH] libopenbios: add Forth LE memory access words
by Mark Cave-Ayland 18 Jun '17

18 Jun '17

These are particularly useful when accessing hardware registers from BE hosts. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> --- libopenbios/init.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/libopenbios/init.c b/libopenbios/init.c index aa99608..3ad9505 100644 --- a/libopenbios/init.c +++ b/libopenbios/init.c @@ -15,12 +15,56 @@ */ #include "config.h" +#include "libc/byteorder.h" #include "libopenbios/openbios.h" #include "libopenbios/bindings.h" #include "libopenbios/initprogram.h" #define NO_QEMU_PROTOS #include "arch/common/fw_cfg.h" + +/* + * le-w! ( w waddr -- ) + */ + +static void lewstore(void) +{ + u16 *aaddr = (u16 *)cell2pointer(POP()); + const u16 word = POP(); + *aaddr = __cpu_to_le16(word); +} + +/* + * le-l! ( quad qaddr -- ) + */ + +static void lelstore(void) +{ + u32 *aaddr = (u32 *)cell2pointer(POP()); + const u32 longval = POP(); + *aaddr = __cpu_to_le32(longval); +} + +/* + * le-w@ ( waddr -- w ) + */ + +static void lewfetch(void) +{ + const u16 *aaddr = (u16 *)cell2pointer(POP()); + PUSH(__le16_to_cpu(*aaddr)); +} + +/* + * le-l@ ( qaddr -- quad ) + */ + +static void lelfetch(void) +{ + const u32 *aaddr = (u32 *)cell2pointer(POP()); + PUSH(__le32_to_cpu(*aaddr)); +} + void openbios_init( void ) { @@ -36,4 +80,10 @@ openbios_init( void ) // Bind the C implementation of (go) into Forth bind_func("(go)", go); + + // Bind the LE access words + bind_func("le-w!", lewstore); + bind_func("le-l!", lelstore); + bind_func("le-w@", lewfetch); + bind_func("le-l@", lelfetch); } -- 1.7.10.4

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