[PATCH] Register Parallel/LPC/FWH programmers

[Carl-Daniel Hailfinger]

Register Parallel/LPC/FWH programmers the same way SPI programmers are
registered.

This patch is not yet 100% clean (80 column limit violations etc.), but
the general idea should be clear.

We need something like this patch to handle programmers with multiple
flash chips (e.g. LPC/FWH chips mapped to different regions on mainboards).

TODO:
- Should register_par_programmer(...) be called before or after setting
max_rom_decode.*?
- Is there a better name for register_par_programmer?
- Should max_rom_decode.* be part of the registration?
- Should map_flash_region/unmap_flash_region be part of the registration?

Please check that all programmers have a register_par_programmer call
unless the chip_* functions were noop.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-register_par_programmer/drkaiser.c
===================================================================
--- flashrom-register_par_programmer/drkaiser.c	(Revision 1325)
+++ flashrom-register_par_programmer/drkaiser.c	(Arbeitskopie)
@@ -37,6 +37,17 @@

static uint8_t *drkaiser_bar;

+static const struct par_programmer par_programmer_drkaiser = {
+		.chip_readb		= drkaiser_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= drkaiser_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
 int drkaiser_init(void)
 {
    uint32_t addr;
@@ -53,7 +64,8 @@
    drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory",
    		       addr, 128 * 1024);

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	register_par_programmer(&par_programmer_drkaiser, CHIP_BUSTYPE_PARALLEL);
+	max_rom_decode.parallel = 131072;

return 0;
 }
Index: flashrom-register_par_programmer/it87spi.c
===================================================================
--- flashrom-register_par_programmer/it87spi.c	(Revision 1325)
+++ flashrom-register_par_programmer/it87spi.c	(Arbeitskopie)
@@ -193,7 +193,7 @@
    free(portpos);
    exit_conf_mode_ite(port);
    it8716f_flashport = flashport;
-	if (buses_supported & CHIP_BUSTYPE_SPI)
+	if (internal_buses_supported & CHIP_BUSTYPE_SPI)
    	msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
    /* FIXME: Add the SPI bus or replace the other buses with it? */
    register_spi_programmer(&spi_programmer_it87xx);
Index: flashrom-register_par_programmer/gfxnvidia.c
===================================================================
--- flashrom-register_par_programmer/gfxnvidia.c	(Revision 1325)
+++ flashrom-register_par_programmer/gfxnvidia.c	(Arbeitskopie)
@@ -60,6 +60,17 @@
    {},
 };

+static const struct par_programmer par_programmer_gfxnvidia = {
+		.chip_readb		= gfxnvidia_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= gfxnvidia_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
 int gfxnvidia_init(void)
 {
    uint32_t reg32;
@@ -78,7 +89,7 @@

nvidia_bar = physmap("NVIDIA", io_base_addr, 16 * 1024 * 1024);

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	register_par_programmer(&par_programmer_gfxnvidia, CHIP_BUSTYPE_PARALLEL);

/* Write/erase doesn't work. */
    programmer_may_write = 0;
Index: flashrom-register_par_programmer/nicrealtek.c
===================================================================
--- flashrom-register_par_programmer/nicrealtek.c	(Revision 1325)
+++ flashrom-register_par_programmer/nicrealtek.c	(Arbeitskopie)
@@ -36,13 +36,24 @@
    {},
 };

+static const struct par_programmer par_programmer_nicrealtek = {
+		.chip_readb             = nicrealtek_chip_readb,
+		.chip_readw             = fallback_chip_readw,
+		.chip_readl             = fallback_chip_readl,
+		.chip_readn             = fallback_chip_readn,
+		.chip_writeb            = nicrealtek_chip_writeb,
+		.chip_writew            = fallback_chip_writew,
+		.chip_writel            = fallback_chip_writel,
+		.chip_writen            = fallback_chip_writen,
+};
+
 int nicrealtek_init(void)
 {
    get_io_perms();

io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek);

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	register_par_programmer(&par_programmer_nicrealtek, CHIP_BUSTYPE_PARALLEL);

return 0;
 }
Index: flashrom-register_par_programmer/serprog.c
===================================================================
--- flashrom-register_par_programmer/serprog.c	(Revision 1325)
+++ flashrom-register_par_programmer/serprog.c	(Arbeitskopie)
@@ -295,6 +295,19 @@
    return 0;
 }

+static const struct par_programmer par_programmer_serprog = {
+		.chip_readb		= serprog_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= serprog_chip_readn,
+		.chip_writeb		= serprog_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
+enum chipbustype serprog_buses_supported = CHIP_BUSTYPE_NONE;
+
 int serprog_init(void)
 {
    uint16_t iface;
@@ -454,7 +467,7 @@
    	msg_perr("Warning: NAK to query supported buses\n");
    	c = CHIP_BUSTYPE_NONSPI;	/* A reasonable default for now. */
    }
-	buses_supported = c;
+	serprog_buses_supported = c;

if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) {
    	msg_perr("Error: NAK to initialize operation buffer\n");
@@ -490,6 +503,8 @@
    	sp_max_read_n = 0;
    }

+	register_par_programmer(&par_programmer_serprog, serprog_buses_supported);
+
    sp_prev_was_write = 0;
    sp_streamed_transmit_ops = 0;
    sp_streamed_transmit_bytes = 0;
Index: flashrom-register_par_programmer/satamv.c
===================================================================
--- flashrom-register_par_programmer/satamv.c	(Revision 1325)
+++ flashrom-register_par_programmer/satamv.c	(Arbeitskopie)
@@ -40,6 +40,17 @@
 #define PCI_BAR2_CONTROL		0x00c08
 #define GPIO_PORT_CONTROL		0x104f0

+static const struct par_programmer par_programmer_satamv = {
+		.chip_readb		= satamv_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= satamv_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
 /*
  * Random notes:
  * FCE#		Flash Chip Enable
@@ -125,7 +136,7 @@
    mv_iobar = tmp & 0xffff;
    msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	register_par_programmer(&par_programmer_satamv, CHIP_BUSTYPE_PARALLEL);

/* 512 kByte with two 8-bit latches, and
     * 4 MByte with additional 3-bit latch. */
Index: flashrom-register_par_programmer/dummyflasher.c
===================================================================
--- flashrom-register_par_programmer/dummyflasher.c	(Revision 1325)
+++ flashrom-register_par_programmer/dummyflasher.c	(Arbeitskopie)
@@ -73,6 +73,20 @@
    .read = default_spi_read,
    .write_256 = dummy_spi_write_256,
 };
+
+static const struct par_programmer par_programmer_dummy = {
+		.chip_readb		= dummy_chip_readb,
+		.chip_readw		= dummy_chip_readw,
+		.chip_readl		= dummy_chip_readl,
+		.chip_readn		= dummy_chip_readn,
+		.chip_writeb		= dummy_chip_writeb,
+		.chip_writew		= dummy_chip_writew,
+		.chip_writel		= dummy_chip_writel,
+		.chip_writen		= dummy_chip_writen,
+};
+
+enum chipbustype dummy_buses_supported = CHIP_BUSTYPE_NONE;
+
 int dummy_init(void)
 {
    char *bustext = NULL;
@@ -90,24 +104,31 @@
    /* Convert the parameters to lowercase. */
    tolower_string(bustext);

-	buses_supported = CHIP_BUSTYPE_NONE;
+	dummy_buses_supported = CHIP_BUSTYPE_NONE;
    if (strstr(bustext, "parallel")) {
-		buses_supported |= CHIP_BUSTYPE_PARALLEL;
+		dummy_buses_supported |= CHIP_BUSTYPE_PARALLEL;
    	msg_pdbg("Enabling support for %s flash.\n", "parallel");
    }
    if (strstr(bustext, "lpc")) {
-		buses_supported |= CHIP_BUSTYPE_LPC;
+		dummy_buses_supported |= CHIP_BUSTYPE_LPC;
    	msg_pdbg("Enabling support for %s flash.\n", "LPC");
    }
    if (strstr(bustext, "fwh")) {
-		buses_supported |= CHIP_BUSTYPE_FWH;
+		dummy_buses_supported |= CHIP_BUSTYPE_FWH;
    	msg_pdbg("Enabling support for %s flash.\n", "FWH");
    }
+	if (dummy_buses_supported & (CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC |
+			       CHIP_BUSTYPE_FWH))
+		register_par_programmer(&par_programmer_dummy,
+					dummy_buses_supported &
+						(CHIP_BUSTYPE_PARALLEL |
+						 CHIP_BUSTYPE_LPC |
+						 CHIP_BUSTYPE_FWH));
    if (strstr(bustext, "spi")) {
    	register_spi_programmer(&spi_programmer_dummyflasher);
    	msg_pdbg("Enabling support for %s flash.\n", "SPI");
    }
-	if (buses_supported == CHIP_BUSTYPE_NONE)
+	if (dummy_buses_supported == CHIP_BUSTYPE_NONE)
    	msg_pdbg("Support for all flash bus types disabled.\n");
    free(bustext);

Index: flashrom-register_par_programmer/internal.c
===================================================================
--- flashrom-register_par_programmer/internal.c	(Revision 1325)
+++ flashrom-register_par_programmer/internal.c	(Arbeitskopie)
@@ -127,6 +127,19 @@
 int is_laptop = 0;
 int laptop_ok = 0;

+static const struct par_programmer par_programmer_internal = {
+		.chip_readb		= internal_chip_readb,
+		.chip_readw		= internal_chip_readw,
+		.chip_readl		= internal_chip_readl,
+		.chip_readn		= internal_chip_readn,
+		.chip_writeb		= internal_chip_writeb,
+		.chip_writew		= internal_chip_writew,
+		.chip_writel		= internal_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
+enum chipbustype internal_buses_supported = CHIP_BUSTYPE_NONE;
+
 int internal_init(void)
 {
 #if __FLASHROM_LITTLE_ENDIAN__
@@ -180,9 +193,10 @@
    get_io_perms();

/* Default to Parallel/LPC/FWH flash devices. If a known host controller
-	 * is found, the init routine sets the buses_supported bitfield.
+	 * is found, the host controller init routine sets the
+	 * internal_buses_supported bitfield.
     */
-	buses_supported = CHIP_BUSTYPE_NONSPI;
+	internal_buses_supported = CHIP_BUSTYPE_NONSPI;

/* Initialize PCI access for flash enables */
    pacc = pci_alloc();	/* Get the pci_access structure */
@@ -267,6 +281,11 @@
     * Besides that, we don't check the board enable return code either.
     */
 #if defined(__i386__) || defined(__x86_64__) || defined (__mips)
+	register_par_programmer(&par_programmer_internal, internal_buses_supported);
+	/* FIXME: Move this message out of chipset_enable.c. */
+	msg_pinfo("This chipset supports the following protocols: %s.\n",
+	       flashbuses_to_text(buses_supported));
+
    return 0;
 #else
    msg_perr("Your platform is not supported yet for the internal "
Index: flashrom-register_par_programmer/nicnatsemi.c
===================================================================
--- flashrom-register_par_programmer/nicnatsemi.c	(Revision 1325)
+++ flashrom-register_par_programmer/nicnatsemi.c	(Arbeitskopie)
@@ -35,13 +35,24 @@
    {},
 };

+static const struct par_programmer par_programmer_nicnatsemi = {
+		.chip_readb             = nicnatsemi_chip_readb,
+		.chip_readw             = fallback_chip_readw,
+		.chip_readl             = fallback_chip_readl,
+		.chip_readn             = fallback_chip_readn,
+		.chip_writeb            = nicnatsemi_chip_writeb,
+		.chip_writew            = fallback_chip_writew,
+		.chip_writel            = fallback_chip_writel,
+		.chip_writen            = fallback_chip_writen,
+};
+
 int nicnatsemi_init(void)
 {
    get_io_perms();

io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi);

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	register_par_programmer(&par_programmer_nicnatsemi, CHIP_BUSTYPE_PARALLEL);

/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
     * in another. My NIC has MA16 connected to A16 on the boot ROM socket
Index: flashrom-register_par_programmer/it85spi.c
===================================================================
--- flashrom-register_par_programmer/it85spi.c	(Revision 1325)
+++ flashrom-register_par_programmer/it85spi.c	(Arbeitskopie)
@@ -254,7 +254,11 @@
    INDIRECT_A3(shm_io_base, (base >> 24));
 #endif
 #ifdef LPC_MEMORY
-	base = (chipaddr)programmer_map_flash_region("it85 communication",
+	/* WTF?!? FIXME: This should use physmap instead. And it should
+	 * automatically block accessing that region for anything else.
+	 * Major TODO here, and it will be a lot of work.
+	 */
+	base = (chipaddr)physmap("it85 communication",
    					     0xFFFFF000, 0x1000);
    msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
             (unsigned int)base);
@@ -282,16 +286,17 @@
 {
    int ret;

-	if (!(buses_supported & CHIP_BUSTYPE_FWH)) {
+	if (!(internal_buses_supported & CHIP_BUSTYPE_FWH)) {
    	msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
    	return 1;
    }
    ret = it85xx_spi_common_init(s);
    msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret);
    if (!ret) {
-		msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__,
-		          buses_supported);
-		if (buses_supported & CHIP_BUSTYPE_FWH)
+		msg_pdbg("%s():%d internal_buses_supported=0x%x\n", __func__, __LINE__,
+		          internal_buses_supported);
+		/* FIXME: We check for FWH, but claim SPI override? WTF? */
+		if (internal_buses_supported & CHIP_BUSTYPE_FWH)
    		msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
    	/* Really leave FWH enabled? */
    	/* Set this as spi controller. */
Index: flashrom-register_par_programmer/atahpt.c
===================================================================
--- flashrom-register_par_programmer/atahpt.c	(Revision 1325)
+++ flashrom-register_par_programmer/atahpt.c	(Arbeitskopie)
@@ -38,6 +38,17 @@
    {},
 };

+static const struct par_programmer par_programmer_atahpt = {
+		.chip_readb		= atahpt_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= atahpt_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
 int atahpt_init(void)
 {
    uint32_t reg32;
@@ -51,7 +62,7 @@
    reg32 |= (1 << 24);
    rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32);

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	register_par_programmer(&par_programmer_atahpt, CHIP_BUSTYPE_PARALLEL);

return 0;
 }
Index: flashrom-register_par_programmer/nic3com.c
===================================================================
--- flashrom-register_par_programmer/nic3com.c	(Revision 1325)
+++ flashrom-register_par_programmer/nic3com.c	(Arbeitskopie)
@@ -55,6 +55,17 @@
    {},
 };

+static const struct par_programmer par_programmer_nic3com = {
+		.chip_readb		= nic3com_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= nic3com_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
 int nic3com_init(void)
 {
    get_io_perms();
@@ -81,8 +92,8 @@
     */
    OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
    max_rom_decode.parallel = 128 * 1024;
+	register_par_programmer(&par_programmer_nic3com, CHIP_BUSTYPE_PARALLEL);

return 0;
 }
Index: flashrom-register_par_programmer/satasii.c
===================================================================
--- flashrom-register_par_programmer/satasii.c	(Revision 1325)
+++ flashrom-register_par_programmer/satasii.c	(Arbeitskopie)
@@ -40,6 +40,17 @@
    {},
 };

+static const struct par_programmer par_programmer_satasii = {
+		.chip_readb		= satasii_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= satasii_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
 int satasii_init(void)
 {
    uint32_t addr;
@@ -65,7 +76,7 @@
    if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
    	msg_pinfo("Warning: Flash seems unconnected.\n");

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	register_par_programmer(&par_programmer_satasii, CHIP_BUSTYPE_PARALLEL);

return 0;
 }
Index: flashrom-register_par_programmer/nicintel.c
===================================================================
--- flashrom-register_par_programmer/nicintel.c	(Revision 1325)
+++ flashrom-register_par_programmer/nicintel.c	(Arbeitskopie)
@@ -41,6 +41,17 @@

#define CSR_FCR 0x0c

+static const struct par_programmer par_programmer_nicintel = {
+		.chip_readb		= nicintel_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= nicintel_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
 int nicintel_init(void)
 {
    uintptr_t addr;
@@ -78,9 +89,8 @@
     */
    pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
-
    max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
+	register_par_programmer(&par_programmer_nicintel, CHIP_BUSTYPE_PARALLEL);

return 0;

Index: flashrom-register_par_programmer/chipset_enable.c
===================================================================
--- flashrom-register_par_programmer/chipset_enable.c	(Revision 1325)
+++ flashrom-register_par_programmer/chipset_enable.c	(Arbeitskopie)
@@ -208,7 +208,7 @@
    uint16_t old, new;
    uint16_t xbcs = 0x4e;	/* X-Bus Chip Select register. */

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	internal_buses_supported = CHIP_BUSTYPE_PARALLEL;

old = pci_read_word(dev, xbcs);

@@ -286,7 +286,7 @@
     * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
     * FB_DEC_EN2.
     */
-	buses_supported = CHIP_BUSTYPE_FWH;
+	internal_buses_supported = CHIP_BUSTYPE_FWH;
    return enable_flash_ich(dev, name, 0x4e);
 }

@@ -383,9 +383,9 @@
    msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);

/* If we're called by enable_flash_ich_dc_spi, it will override
-	 * buses_supported anyway.
+	 * internal_buses_supported anyway.
     */
-	buses_supported = CHIP_BUSTYPE_FWH;
+	internal_buses_supported = CHIP_BUSTYPE_FWH;
    return enable_flash_ich(dev, name, 0xdc);
 }

@@ -405,7 +405,7 @@
        if (new != old)
                rpci_write_byte(dev, 0xd9, new);

-	buses_supported = CHIP_BUSTYPE_FWH;
+	internal_buses_supported = CHIP_BUSTYPE_FWH;
        return 0;
 }

@@ -458,7 +458,7 @@
     * on ICH7 when the southbridge is strapped to LPC
     */

-	buses_supported = CHIP_BUSTYPE_FWH;
+	internal_buses_supported = CHIP_BUSTYPE_FWH;
    if (ich_generation == 7) {
    	if(bbs == ICH_STRAP_LPC) {
    		/* No further SPI initialization required */
@@ -466,7 +466,7 @@
    	}
    	else
    		/* Disable LPC/FWH if strapped to PCI or SPI */
-			buses_supported = 0;
+			internal_buses_supported = 0;
    }

/* this adds CHIP_BUSTYPE_SPI */
@@ -557,7 +557,7 @@
 #define CS5530_ENABLE_SA2320		(1 << 2)
 #define CS5530_ENABLE_SA20		(1 << 6)

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	internal_buses_supported = CHIP_BUSTYPE_PARALLEL;
    /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
     * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
     * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
@@ -707,7 +707,7 @@
    			(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
    }

-	buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
+	internal_buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;

ret = sb600_probe_spi(dev);

@@ -793,7 +793,7 @@
 {
    uint8_t tmp;

-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	internal_buses_supported = CHIP_BUSTYPE_PARALLEL;

tmp = INB(0xc06);
    tmp |= 0x1;
@@ -893,7 +893,7 @@
    switch ((val >> 5) & 0x3) {
    case 0x0:
    	ret = enable_flash_mcp55(dev, name);
-		buses_supported = CHIP_BUSTYPE_LPC;
+		internal_buses_supported = CHIP_BUSTYPE_LPC;
    	msg_pdbg("Flash bus type is LPC\n");
    	break;
    case 0x2:
@@ -901,14 +901,14 @@
    	/* SPI is added in mcp6x_spi_init if it works.
    	 * Do we really want to disable LPC in this case?
    	 */
-		buses_supported = CHIP_BUSTYPE_NONE;
+		internal_buses_supported = CHIP_BUSTYPE_NONE;
    	msg_pdbg("Flash bus type is SPI\n");
    	msg_perr("SPI on this chipset is WIP. Write is unsupported!\n");
    	programmer_may_write = 0;
    	break;
    default:
    	/* Should not happen. */
-		buses_supported = CHIP_BUSTYPE_NONE;
+		internal_buses_supported = CHIP_BUSTYPE_NONE;
    	msg_pdbg("Flash bus type is unknown (none)\n");
    	msg_pinfo("Something went wrong with bus type detection.\n");
    	goto out_msg;
@@ -1215,8 +1215,5 @@
    		msg_pinfo("PROBLEMS, continuing anyway\n");
    }

-	msg_pinfo("This chipset supports the following protocols: %s.\n",
-	       flashbuses_to_text(buses_supported));
-
    return ret;
 }
Index: flashrom-register_par_programmer/programmer.c
===================================================================
--- flashrom-register_par_programmer/programmer.c	(Revision 1325)
+++ flashrom-register_par_programmer/programmer.c	(Arbeitskopie)
@@ -19,7 +19,21 @@
  */

#include "flash.h"
+#include "programmer.h"

+static const struct par_programmer par_programmer_none = {
+		.chip_readb		= noop_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= noop_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+};
+
+const struct par_programmer *par_programmer = &par_programmer_none;
+
 /* No-op shutdown() for programmers which don't need special handling */
 int noop_shutdown(void)
 {
@@ -96,3 +110,9 @@
    	buf[i] = chip_readb(addr + i);
    return;
 }
+
+void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses)
+{
+	par_programmer = pgm;
+	buses_supported |= buses;
+}
Index: flashrom-register_par_programmer/flashrom.c
===================================================================
--- flashrom-register_par_programmer/flashrom.c	(Revision 1325)
+++ flashrom-register_par_programmer/flashrom.c	(Arbeitskopie)
@@ -132,14 +132,6 @@
    	.shutdown		= internal_shutdown,
    	.map_flash_region	= physmap,
    	.unmap_flash_region	= physunmap,
-		.chip_readb		= internal_chip_readb,
-		.chip_readw		= internal_chip_readw,
-		.chip_readl		= internal_chip_readl,
-		.chip_readn		= internal_chip_readn,
-		.chip_writeb		= internal_chip_writeb,
-		.chip_writew		= internal_chip_writew,
-		.chip_writel		= internal_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -151,14 +143,6 @@
    	.shutdown		= dummy_shutdown,
    	.map_flash_region	= dummy_map,
    	.unmap_flash_region	= dummy_unmap,
-		.chip_readb		= dummy_chip_readb,
-		.chip_readw		= dummy_chip_readw,
-		.chip_readl		= dummy_chip_readl,
-		.chip_readn		= dummy_chip_readn,
-		.chip_writeb		= dummy_chip_writeb,
-		.chip_writew		= dummy_chip_writew,
-		.chip_writel		= dummy_chip_writel,
-		.chip_writen		= dummy_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -170,14 +154,6 @@
    	.shutdown		= nic3com_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= nic3com_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= nic3com_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -191,14 +167,6 @@
    	.shutdown               = nicrealtek_shutdown,
    	.map_flash_region       = fallback_map,
    	.unmap_flash_region     = fallback_unmap,
-		.chip_readb             = nicrealtek_chip_readb,
-		.chip_readw             = fallback_chip_readw,
-		.chip_readl             = fallback_chip_readl,
-		.chip_readn             = fallback_chip_readn,
-		.chip_writeb            = nicrealtek_chip_writeb,
-		.chip_writew            = fallback_chip_writew,
-		.chip_writel            = fallback_chip_writel,
-		.chip_writen            = fallback_chip_writen,
    	.delay                  = internal_delay,
    },
 #endif
@@ -210,14 +178,6 @@
    	.shutdown               = nicnatsemi_shutdown,
    	.map_flash_region       = fallback_map,
    	.unmap_flash_region     = fallback_unmap,
-		.chip_readb             = nicnatsemi_chip_readb,
-		.chip_readw             = fallback_chip_readw,
-		.chip_readl             = fallback_chip_readl,
-		.chip_readn             = fallback_chip_readn,
-		.chip_writeb            = nicnatsemi_chip_writeb,
-		.chip_writew            = fallback_chip_writew,
-		.chip_writel            = fallback_chip_writel,
-		.chip_writen            = fallback_chip_writen,
    	.delay                  = internal_delay,
    },
 #endif
@@ -229,14 +189,6 @@
    	.shutdown		= gfxnvidia_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= gfxnvidia_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= gfxnvidia_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -248,14 +200,6 @@
    	.shutdown		= drkaiser_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= drkaiser_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= drkaiser_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -267,14 +211,6 @@
    	.shutdown		= satasii_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= satasii_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= satasii_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -286,14 +222,6 @@
    	.shutdown		= atahpt_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= atahpt_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= atahpt_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -305,14 +233,6 @@
    	.shutdown		= noop_shutdown, /* Missing shutdown */
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= noop_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= noop_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -324,14 +244,6 @@
    	.shutdown		= serprog_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= serprog_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= serprog_chip_readn,
-		.chip_writeb		= serprog_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= serprog_delay,
    },
 #endif
@@ -343,14 +255,6 @@
    	.shutdown		= buspirate_spi_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= noop_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= noop_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -362,14 +266,6 @@
    	.shutdown		= dediprog_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= noop_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= noop_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -381,14 +277,6 @@
    	.shutdown		= noop_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= noop_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= noop_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -400,14 +288,6 @@
    	.shutdown		= nicintel_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= nicintel_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= nicintel_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -419,14 +299,6 @@
    	.shutdown = nicintel_spi_shutdown,
    	.map_flash_region = fallback_map,
    	.unmap_flash_region = fallback_unmap,
-		.chip_readb = noop_chip_readb,
-		.chip_readw = fallback_chip_readw,
-		.chip_readl = fallback_chip_readl,
-		.chip_readn = fallback_chip_readn,
-		.chip_writeb = noop_chip_writeb,
-		.chip_writew = fallback_chip_writew,
-		.chip_writel = fallback_chip_writel,
-		.chip_writen = fallback_chip_writen,
    	.delay = internal_delay,
    },
 #endif
@@ -438,14 +310,6 @@
    	.shutdown = ogp_spi_shutdown,
    	.map_flash_region = fallback_map,
    	.unmap_flash_region = fallback_unmap,
-		.chip_readb = noop_chip_readb,
-		.chip_readw = fallback_chip_readw,
-		.chip_readl = fallback_chip_readl,
-		.chip_readn = fallback_chip_readn,
-		.chip_writeb = noop_chip_writeb,
-		.chip_writew = fallback_chip_writew,
-		.chip_writel = fallback_chip_writel,
-		.chip_writen = fallback_chip_writen,
    	.delay = internal_delay,
    },
 #endif
@@ -457,14 +321,6 @@
    	.shutdown		= satamv_shutdown,
    	.map_flash_region	= fallback_map,
    	.unmap_flash_region	= fallback_unmap,
-		.chip_readb		= satamv_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= satamv_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
    	.delay			= internal_delay,
    },
 #endif
@@ -566,42 +422,42 @@

void chip_writeb(uint8_t val, chipaddr addr)
 {
-	programmer_table[programmer].chip_writeb(val, addr);
+	par_programmer->chip_writeb(val, addr);
 }

void chip_writew(uint16_t val, chipaddr addr)
 {
-	programmer_table[programmer].chip_writew(val, addr);
+	par_programmer->chip_writew(val, addr);
 }

void chip_writel(uint32_t val, chipaddr addr)
 {
-	programmer_table[programmer].chip_writel(val, addr);
+	par_programmer->chip_writel(val, addr);
 }

void chip_writen(uint8_t *buf, chipaddr addr, size_t len)
 {
-	programmer_table[programmer].chip_writen(buf, addr, len);
+	par_programmer->chip_writen(buf, addr, len);
 }

uint8_t chip_readb(const chipaddr addr)
 {
-	return programmer_table[programmer].chip_readb(addr);
+	return par_programmer->chip_readb(addr);
 }

uint16_t chip_readw(const chipaddr addr)
 {
-	return programmer_table[programmer].chip_readw(addr);
+	return par_programmer->chip_readw(addr);
 }

uint32_t chip_readl(const chipaddr addr)
 {
-	return programmer_table[programmer].chip_readl(addr);
+	return par_programmer->chip_readl(addr);
 }

void chip_readn(uint8_t *buf, chipaddr addr, size_t len)
 {
-	programmer_table[programmer].chip_readn(buf, addr, len);
+	par_programmer->chip_readn(buf, addr, len);
 }

void programmer_delay(int usecs)
Index: flashrom-register_par_programmer/programmer.h
===================================================================
--- flashrom-register_par_programmer/programmer.h	(Revision 1325)
+++ flashrom-register_par_programmer/programmer.h	(Arbeitskopie)
@@ -95,14 +95,6 @@
    			    size_t len);
    void (*unmap_flash_region) (void *virt_addr, size_t len);

-	void (*chip_writeb) (uint8_t val, chipaddr addr);
-	void (*chip_writew) (uint16_t val, chipaddr addr);
-	void (*chip_writel) (uint32_t val, chipaddr addr);
-	void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
-	uint8_t (*chip_readb) (const chipaddr addr);
-	uint16_t (*chip_readw) (const chipaddr addr);
-	uint32_t (*chip_readl) (const chipaddr addr);
-	void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
    void (*delay) (int usecs);
 };

@@ -302,6 +294,7 @@
 extern int force_boardmismatch;
 void probe_superio(void);
 int register_superio(struct superio s);
+extern enum chipbustype internal_buses_supported;
 int internal_init(void);
 int internal_shutdown(void);
 void internal_chip_writeb(uint8_t val, chipaddr addr);
@@ -357,6 +350,18 @@
 uint16_t fallback_chip_readw(const chipaddr addr);
 uint32_t fallback_chip_readl(const chipaddr addr);
 void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
+struct par_programmer {
+	void (*chip_writeb) (uint8_t val, chipaddr addr);
+	void (*chip_writew) (uint16_t val, chipaddr addr);
+	void (*chip_writel) (uint32_t val, chipaddr addr);
+	void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
+	uint8_t (*chip_readb) (const chipaddr addr);
+	uint16_t (*chip_readw) (const chipaddr addr);
+	uint32_t (*chip_readl) (const chipaddr addr);
+	void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
+};
+extern const struct par_programmer *par_programmer;
+void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses);

/* dummyflasher.c */
 #if CONFIG_DUMMY == 1
Index: flashrom-register_par_programmer/board_enable.c
===================================================================
--- flashrom-register_par_programmer/board_enable.c	(Revision 1325)
+++ flashrom-register_par_programmer/board_enable.c	(Arbeitskopie)
@@ -424,7 +424,7 @@
    /* Check if at least one flash segment is enabled. */
    if (tmp & 0xf0) {
    	/* The IT8705F will respond to LPC cycles and translate them. */
-		buses_supported = CHIP_BUSTYPE_PARALLEL;
+		internal_buses_supported = CHIP_BUSTYPE_PARALLEL;
    	/* Flash ROM I/F Writes Enable */
    	tmp |= 0x04;
    	msg_pdbg("Enabling IT8705F flash ROM interface write.\n");