[PATCH] Try to handle non-x86 sanely
flashrom is very x86 centric. It does work on other architectures if you get it to compile. Try to fix the worst compile errors on non-x86 for a full build. Should work in theory with a default build if you exclude nic3com. Will pretty sure break compilation on Alpha. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Index: flashrom-ioport_x86_only/hwaccess.c =================================================================== --- flashrom-ioport_x86_only/hwaccess.c (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.c (Arbeitskopie) @@ -26,6 +26,8 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,6 +56,22 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + #ifdef __DJGPP__ extern unsigned short segFS; Index: flashrom-ioport_x86_only/hwaccess.h =================================================================== --- flashrom-ioport_x86_only/hwaccess.h (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.h (Arbeitskopie) @@ -31,6 +31,8 @@ #include <pci/pci.h> #endif +#if defined(__i386__) || defined(__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +164,11 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +/* Port I/O is not available on PowerPC. */ + +#else +#error Unknown architecture +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-ioport_x86_only/it87spi.c =================================================================== --- flashrom-ioport_x86_only/it87spi.c (Revision 984) +++ flashrom-ioport_x86_only/it87spi.c (Arbeitskopie) @@ -29,6 +29,8 @@ #include "chipdrivers.h" #include "spi.h" +#if defined(__i386__) || defined(__x86_64__) + #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e @@ -347,3 +349,5 @@ return 0; } + +#endif Index: flashrom-ioport_x86_only/physmap.c =================================================================== --- flashrom-ioport_x86_only/physmap.c (Revision 984) +++ flashrom-ioport_x86_only/physmap.c (Arbeitskopie) @@ -238,6 +238,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -455,4 +457,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-ioport_x86_only/nic3com.c =================================================================== --- flashrom-ioport_x86_only/nic3com.c (Revision 984) +++ flashrom-ioport_x86_only/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unknown architecture +#endif Index: flashrom-ioport_x86_only/wbsio_spi.c =================================================================== --- flashrom-ioport_x86_only/wbsio_spi.c (Revision 984) +++ flashrom-ioport_x86_only/wbsio_spi.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include "chipdrivers.h" #include "spi.h" +#if defined(__i386__) || defined(__x86_64__) + #define WBSIO_PORT1 0x2e #define WBSIO_PORT2 0x4e @@ -199,3 +201,5 @@ return spi_chip_write_1(flash, buf); } + +#endif Index: flashrom-ioport_x86_only/chipset_enable.c =================================================================== --- flashrom-ioport_x86_only/chipset_enable.c (Revision 984) +++ flashrom-ioport_x86_only/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1417,7 +1422,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-ioport_x86_only/board_enable.c =================================================================== --- flashrom-ioport_x86_only/board_enable.c (Revision 984) +++ flashrom-ioport_x86_only/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1299,6 +1300,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1342,6 +1345,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1407,7 +1411,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/
Misha Manulis asked for satasii support on PPC and on IRC we gave him some hints to hack up something that works for ppc only and satasii only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA Here is a patch which does everything The Right Way (TM) and uses proper abstraction for satasii and compiles all x86 specific stuff only on x86. Huge thanks go to Segher Boessenkool who provided valuable info about all the endianness trickery (especially preprocessor macros) and tested 8 iterations of the code on Linux/PPC. On 26.03.2010 01:51, Carl-Daniel Hailfinger wrote:
flashrom is very x86 centric. It does work on other architectures if you get it to compile. Try to fix the all errors on ppc for a full build.
Should work in theory with a default build if you exclude nic3com. Will pretty sure break compilation on Alpha.
This one should compile on ppc, I even expect it to work for satasii on ppc. AFAICS all programmer drivers except nic3com should work. Compile with make distclean make NIC3COM=no Known bugs: x86 is broken by this patch because the Makefile excludes the x86 specific internal files. If you want to test this patch on x86 (to make sure I didn't break everything), change #PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o to PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o boards_ok and boards_bad has no x86 guard yet and will end up in flashrom -L output. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Index: flashrom-ioport_x86_only/hwaccess.c =================================================================== --- flashrom-ioport_x86_only/hwaccess.c (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.c (Arbeitskopie) @@ -26,6 +26,8 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,6 +56,22 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + #ifdef __DJGPP__ extern unsigned short segFS; @@ -122,3 +140,33 @@ return *(volatile uint32_t *) addr; } #endif + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writeb(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writeb(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-ioport_x86_only/flash.h =================================================================== --- flashrom-ioport_x86_only/flash.h (Revision 984) +++ flashrom-ioport_x86_only/flash.h (Arbeitskopie) @@ -59,8 +59,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -402,6 +404,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -585,6 +593,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -592,6 +601,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-ioport_x86_only/spi25.c =================================================================== --- flashrom-ioport_x86_only/spi25.c (Revision 984) +++ flashrom-ioport_x86_only/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -950,11 +952,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-ioport_x86_only/hwaccess.h =================================================================== --- flashrom-ioport_x86_only/hwaccess.h (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.h (Arbeitskopie) @@ -24,13 +24,88 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#define ___constant_swab8(x) ((uint8_t)( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#else + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +237,11 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +/* Port I/O is not available on PowerPC. */ + +#else +#error Unknown architecture +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-ioport_x86_only/physmap.c =================================================================== --- flashrom-ioport_x86_only/physmap.c (Revision 984) +++ flashrom-ioport_x86_only/physmap.c (Arbeitskopie) @@ -238,6 +238,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -455,4 +457,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-ioport_x86_only/spi.c =================================================================== --- flashrom-ioport_x86_only/spi.c (Revision 984) +++ flashrom-ioport_x86_only/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-ioport_x86_only/nic3com.c =================================================================== --- flashrom-ioport_x86_only/nic3com.c (Revision 984) +++ flashrom-ioport_x86_only/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unknown architecture +#endif Index: flashrom-ioport_x86_only/Makefile =================================================================== --- flashrom-ioport_x86_only/Makefile (Revision 984) +++ flashrom-ioport_x86_only/Makefile (Arbeitskopie) @@ -121,7 +121,8 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +#PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -253,7 +254,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-ioport_x86_only/satasii.c =================================================================== --- flashrom-ioport_x86_only/satasii.c (Revision 984) +++ flashrom-ioport_x86_only/satasii.c (Arbeitskopie) @@ -62,7 +62,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -82,32 +82,32 @@ { uint32_t ctrl_reg, data_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val; + mmio_le_writel(data_reg, (sii_bar + 4)); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - mmio_writel(ctrl_reg, sii_bar); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; - return (mmio_readl(sii_bar + 4)) & 0xff; + return (mmio_le_readl(sii_bar + 4)) & 0xff; } Index: flashrom-ioport_x86_only/chipset_enable.c =================================================================== --- flashrom-ioport_x86_only/chipset_enable.c (Revision 984) +++ flashrom-ioport_x86_only/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1417,7 +1422,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-ioport_x86_only/flashrom.c =================================================================== --- flashrom-ioport_x86_only/flashrom.c (Revision 984) +++ flashrom-ioport_x86_only/flashrom.c (Arbeitskopie) @@ -233,6 +233,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -250,6 +251,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { Index: flashrom-ioport_x86_only/internal.c =================================================================== --- flashrom-ioport_x86_only/internal.c (Revision 984) +++ flashrom-ioport_x86_only/internal.c (Arbeitskopie) @@ -99,9 +99,11 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -111,8 +113,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -149,10 +152,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) @@ -173,8 +179,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-ioport_x86_only/board_enable.c =================================================================== --- flashrom-ioport_x86_only/board_enable.c (Revision 984) +++ flashrom-ioport_x86_only/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1299,6 +1300,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1342,6 +1345,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1407,7 +1411,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/
On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote:
Misha Manulis asked for satasii support on PPC and on IRC we gave him some hints to hack up something that works for ppc only and satasii only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA
Here is a patch which does everything The Right Way (TM) and uses proper abstraction for satasii and compiles all x86 specific stuff only on x86.
Huge thanks go to Segher Boessenkool who provided valuable info about all the endianness trickery (especially preprocessor macros) and tested 8 iterations of the code on Linux/PPC.
On 26.03.2010 01:51, Carl-Daniel Hailfinger wrote:
flashrom is very x86 centric. It does work on other architectures if you get it to compile. Try to fix the all errors on ppc for a full build.
Should work in theory with a default build if you exclude nic3com. Will pretty sure break compilation on Alpha.
This one should compile on ppc, I even expect it to work for satasii on ppc. AFAICS all programmer drivers except nic3com should work. Compile with make distclean make NIC3COM=no
Known bugs:
x86 is broken by this patch because the Makefile excludes the x86 specific internal files. If you want to test this patch on x86 (to make sure I didn't break everything), change #PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o to PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
boards_ok and boards_bad has no x86 guard yet and will end up in flashrom -L output.
Misha Manulis tested the patch and it didn't work. I found a typo which truncated all 16 bit and 32 bit LE write accesses to 8 bit. New version, should work fine with the x86/nic3com exceptions mentioned above. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Index: flashrom-ioport_x86_only/hwaccess.c =================================================================== --- flashrom-ioport_x86_only/hwaccess.c (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.c (Arbeitskopie) @@ -26,6 +26,8 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,6 +56,22 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + #ifdef __DJGPP__ extern unsigned short segFS; @@ -122,3 +140,33 @@ return *(volatile uint32_t *) addr; } #endif + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-ioport_x86_only/flash.h =================================================================== --- flashrom-ioport_x86_only/flash.h (Revision 984) +++ flashrom-ioport_x86_only/flash.h (Arbeitskopie) @@ -59,8 +59,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -402,6 +404,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -585,6 +593,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -592,6 +601,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-ioport_x86_only/spi25.c =================================================================== --- flashrom-ioport_x86_only/spi25.c (Revision 984) +++ flashrom-ioport_x86_only/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -950,11 +952,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-ioport_x86_only/hwaccess.h =================================================================== --- flashrom-ioport_x86_only/hwaccess.h (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.h (Arbeitskopie) @@ -24,13 +24,88 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#define ___constant_swab8(x) ((uint8_t)( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#else + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +237,11 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +/* Port I/O is not available on PowerPC. */ + +#else +#error Unknown architecture +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-ioport_x86_only/physmap.c =================================================================== --- flashrom-ioport_x86_only/physmap.c (Revision 984) +++ flashrom-ioport_x86_only/physmap.c (Arbeitskopie) @@ -238,6 +238,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -455,4 +457,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-ioport_x86_only/spi.c =================================================================== --- flashrom-ioport_x86_only/spi.c (Revision 984) +++ flashrom-ioport_x86_only/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-ioport_x86_only/nic3com.c =================================================================== --- flashrom-ioport_x86_only/nic3com.c (Revision 984) +++ flashrom-ioport_x86_only/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unknown architecture +#endif Index: flashrom-ioport_x86_only/Makefile =================================================================== --- flashrom-ioport_x86_only/Makefile (Revision 984) +++ flashrom-ioport_x86_only/Makefile (Arbeitskopie) @@ -121,7 +121,8 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +#PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -253,7 +254,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-ioport_x86_only/satasii.c =================================================================== --- flashrom-ioport_x86_only/satasii.c (Revision 984) +++ flashrom-ioport_x86_only/satasii.c (Arbeitskopie) @@ -62,7 +62,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -82,32 +82,32 @@ { uint32_t ctrl_reg, data_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val; + mmio_le_writel(data_reg, (sii_bar + 4)); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - mmio_writel(ctrl_reg, sii_bar); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; - return (mmio_readl(sii_bar + 4)) & 0xff; + return (mmio_le_readl(sii_bar + 4)) & 0xff; } Index: flashrom-ioport_x86_only/chipset_enable.c =================================================================== --- flashrom-ioport_x86_only/chipset_enable.c (Revision 984) +++ flashrom-ioport_x86_only/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1417,7 +1422,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-ioport_x86_only/flashrom.c =================================================================== --- flashrom-ioport_x86_only/flashrom.c (Revision 984) +++ flashrom-ioport_x86_only/flashrom.c (Arbeitskopie) @@ -233,6 +233,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -250,6 +251,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { Index: flashrom-ioport_x86_only/internal.c =================================================================== --- flashrom-ioport_x86_only/internal.c (Revision 984) +++ flashrom-ioport_x86_only/internal.c (Arbeitskopie) @@ -99,9 +99,11 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -111,8 +113,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -149,10 +152,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) @@ -173,8 +179,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-ioport_x86_only/board_enable.c =================================================================== --- flashrom-ioport_x86_only/board_enable.c (Revision 984) +++ flashrom-ioport_x86_only/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1299,6 +1300,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1342,6 +1345,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1407,7 +1411,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/
I tested the changes on my system. The system is a CurtisWright Raptor board with a single PowerPC 7457 processor. It has a daughter-board from TechnoBox 5575 PCI-over-PMC SATA adapter. The daughter-board has onboard BIOS (AMD flash chip) and EEPROM. I was able to read, write and erase both chips using satasii programmer. I did encounter an issue when my rootfs is mounted over NFS. When writing data back onto flash, the data came back in reverse endianness from the original. This was only an issue with NFS-mounted rootfs. When I tested the same procedure with the rootfs mounted from the internal SATA drive, everything was consistent. My test procedure was as follows: 1. Run flashrom to detect the flah chips flashrom -p satasii 2. Got the contents of the flash chips and diff-ed the hexdump of the contents against a known good image which came back with no differences flashrom -p satasii -r current_contents.img 3. Erased the contents of flash. Dumped the contents of the flash after erase and verified that it is all zeros (0) flashrom -p satasii -E 4. Flashed the contents of the known good image flashrom -p satasii -w original.img 5. Dumped the new contents and verified the hexdump against the known good image again Log of the steps and their result: vsm:~# ./flashrom -p satasii flashrom v0.9.1-r985 Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0). === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom@flashrom.org if it works for you. Thank you for your help! === Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100. Warning: Flash seems unconnected. Calibrating delay loop... OK. Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. vsm:~# ./flashrom -p satasii -r current_contents.img flashrom v0.9.1-r985 Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0). === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom@flashrom.org if it works for you. Thank you for your help! === Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100. Warning: Flash seems unconnected. Calibrating delay loop... OK. Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Reading flash... done. vsm:~# hexdump current_contents.img > current_contents.hex vsm:~# diff sii.hex current_contents.hex vsm:~# ./flashrom -p satasii -E flashrom v0.9.1-r985 Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0). === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom@flashrom.org if it works for you. Thank you for your help! === Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100. Warning: Flash seems unconnected. Calibrating delay loop... OK. Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Erasing flash chip... SUCCESS. vsm:~# ./flashrom -p satasii -r empty.img flashrom v0.9.1-r985 Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0). === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom@flashrom.org if it works for you. Thank you for your help! === Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100. Warning: Flash seems unconnected. Calibrating delay loop... OK. Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Reading flash... done. vsm:~# hexdump empty.img 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0080000 vsm:~# ./flashrom -p satasii -w sii. sii.dump sii.hex vsm:~# ./flashrom -p satasii -w sii.dump flashrom v0.9.1-r985 Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0). === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom@flashrom.org if it works for you. Thank you for your help! === Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100. Warning: Flash seems unconnected. Calibrating delay loop... OK. Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... SUCCESS. Programming page: DONE!ss: 0x0007f000 COMPLETE. Verifying flash... VERIFIED. vsm:~# ./flashrom -p satasii -r new.img flashrom v0.9.1-r985 Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0). === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom@flashrom.org if it works for you. Thank you for your help! === Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100. Warning: Flash seems unconnected. Calibrating delay loop... OK. Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Reading flash... done. vsm:~# hexdump new.img > new.hex vsm:~# diff new.hex sii.hex All these steps were completed successfully Thank you everyone for your help Acked-by: Misha Manulis <misha@manulis.com> On Fri, Mar 26, 2010 at 9:42 AM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006@gmx.net> wrote:
On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote:
Misha Manulis asked for satasii support on PPC and on IRC we gave him some hints to hack up something that works for ppc only and satasii only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA
Here is a patch which does everything The Right Way (TM) and uses proper abstraction for satasii and compiles all x86 specific stuff only on x86.
Huge thanks go to Segher Boessenkool who provided valuable info about all the endianness trickery (especially preprocessor macros) and tested 8 iterations of the code on Linux/PPC.
On 26.03.2010 01:51, Carl-Daniel Hailfinger wrote:
flashrom is very x86 centric. It does work on other architectures if you get it to compile. Try to fix the all errors on ppc for a full build.
Should work in theory with a default build if you exclude nic3com. Will pretty sure break compilation on Alpha.
This one should compile on ppc, I even expect it to work for satasii on ppc. AFAICS all programmer drivers except nic3com should work. Compile with make distclean make NIC3COM=no
Known bugs:
x86 is broken by this patch because the Makefile excludes the x86 specific internal files. If you want to test this patch on x86 (to make sure I didn't break everything), change #PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o to PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
boards_ok and boards_bad has no x86 guard yet and will end up in flashrom -L output.
Misha Manulis tested the patch and it didn't work. I found a typo which truncated all 16 bit and 32 bit LE write accesses to 8 bit.
New version, should work fine with the x86/nic3com exceptions mentioned above.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Index: flashrom-ioport_x86_only/hwaccess.c =================================================================== --- flashrom-ioport_x86_only/hwaccess.c (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.c (Arbeitskopie) @@ -26,6 +26,8 @@ #include <errno.h> #include "flash.h"
+#if defined(__i386__) || defined(__x86_64__) + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,6 +56,22 @@ #endif }
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + #ifdef __DJGPP__
extern unsigned short segFS; @@ -122,3 +140,33 @@ return *(volatile uint32_t *) addr; } #endif + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-ioport_x86_only/flash.h =================================================================== --- flashrom-ioport_x86_only/flash.h (Revision 984) +++ flashrom-ioport_x86_only/flash.h (Arbeitskopie) @@ -59,8 +59,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -402,6 +404,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr);
/* programmer.c */ int noop_shutdown(void); @@ -585,6 +593,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -592,6 +601,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-ioport_x86_only/spi25.c =================================================================== --- flashrom-ioport_x86_only/spi25.c (Revision 984) +++ flashrom-ioport_x86_only/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -950,11 +952,13 @@
switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-ioport_x86_only/hwaccess.h =================================================================== --- flashrom-ioport_x86_only/hwaccess.h (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.h (Arbeitskopie) @@ -24,13 +24,88 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1
+#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif
+#define ___constant_swab8(x) ((uint8_t)( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#else + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +237,11 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +/* Port I/O is not available on PowerPC. */ + +#else +#error Unknown architecture +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-ioport_x86_only/physmap.c =================================================================== --- flashrom-ioport_x86_only/physmap.c (Revision 984) +++ flashrom-ioport_x86_only/physmap.c (Arbeitskopie) @@ -238,6 +238,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); }
+#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -455,4 +457,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-ioport_x86_only/spi.c =================================================================== --- flashrom-ioport_x86_only/spi.c (Revision 984) +++ flashrom-ioport_x86_only/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ },
#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif
#if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-ioport_x86_only/nic3com.c =================================================================== --- flashrom-ioport_x86_only/nic3com.c (Revision 984) +++ flashrom-ioport_x86_only/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h"
+#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unknown architecture +#endif Index: flashrom-ioport_x86_only/Makefile =================================================================== --- flashrom-ioport_x86_only/Makefile (Revision 984) +++ flashrom-ioport_x86_only/Makefile (Arbeitskopie) @@ -121,7 +121,8 @@
ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +#PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif
@@ -253,7 +254,7 @@ rm -f .dependencies .features .libdeps
dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies
strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-ioport_x86_only/satasii.c =================================================================== --- flashrom-ioport_x86_only/satasii.c (Revision 984) +++ flashrom-ioport_x86_only/satasii.c (Arbeitskopie) @@ -62,7 +62,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;
/* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n");
buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -82,32 +82,32 @@ { uint32_t ctrl_reg, data_reg;
- while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;
/* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
- data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val; + mmio_le_writel(data_reg, (sii_bar + 4)); + mmio_le_writel(ctrl_reg, sii_bar);
- while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; }
uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg;
- while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;
/* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
- mmio_writel(ctrl_reg, sii_bar); + mmio_le_writel(ctrl_reg, sii_bar);
- while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ;
- return (mmio_readl(sii_bar + 4)) & 0xff; + return (mmio_le_readl(sii_bar + 4)) & 0xff; } Index: flashrom-ioport_x86_only/chipset_enable.c =================================================================== --- flashrom-ioport_x86_only/chipset_enable.c (Revision 984) +++ flashrom-ioport_x86_only/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h"
+#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock;
static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; }
+#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1417,7 +1422,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, };
Index: flashrom-ioport_x86_only/flashrom.c =================================================================== --- flashrom-ioport_x86_only/flashrom.c (Revision 984) +++ flashrom-ioport_x86_only/flashrom.c (Arbeitskopie) @@ -233,6 +233,7 @@ #endif
#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -250,6 +251,7 @@ .delay = internal_delay, }, #endif +#endif
#if FT2232_SPI_SUPPORT == 1 { Index: flashrom-ioport_x86_only/internal.c =================================================================== --- flashrom-ioport_x86_only/internal.c (Revision 984) +++ flashrom-ioport_x86_only/internal.c (Arbeitskopie) @@ -99,9 +99,11 @@ #endif
#if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0;
+#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -111,8 +113,9 @@ superio = probe_superio_winbond(); #endif } +#endif
-int is_laptop; +int is_laptop = 0;
int internal_init(void) { @@ -149,10 +152,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init();
/* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif
/* Warn if a laptop is detected. */ if (is_laptop) @@ -173,8 +179,10 @@ "will most likely fail.\n"); }
+#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif
board_flash_enable(lb_vendor, lb_part);
Index: flashrom-ioport_x86_only/board_enable.c =================================================================== --- flashrom-ioport_x86_only/board_enable.c (Revision 984) +++ flashrom-ioport_x86_only/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h"
+#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1299,6 +1300,8 @@ return it8712f_gpio_set(32, 1); }
+#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1342,6 +1345,7 @@ struct board_pciid_enable board_pciid_enables[] = {
/* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1407,7 +1411,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ };
On 26.03.2010 19:13, Michael Manulis wrote:
I tested the changes on my system. The system is a CurtisWright Raptor board with a single PowerPC 7457 processor. It has a daughter-board from TechnoBox 5575 PCI-over-PMC SATA adapter. The daughter-board has onboard BIOS (AMD flash chip) and EEPROM.
I was able to read, write and erase both chips using satasii programmer.
I did encounter an issue when my rootfs is mounted over NFS. When writing data back onto flash, the data came back in reverse endianness from the original. This was only an issue with NFS-mounted rootfs. When I tested the same procedure with the rootfs mounted from the internal SATA drive, everything was consistent. [...]
vsm:~# ./flashrom -p satasii flashrom v0.9.1-r985 Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0). === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom@flashrom.org if it works for you. Thank you for your help! === Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100. Warning: Flash seems unconnected. Calibrating delay loop... OK. Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000.
Acked-by: Misha Manulis <misha@manulis.com>
On Fri, Mar 26, 2010 at 9:42 AM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006@gmx.net> wrote:
On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote:
Misha Manulis asked for satasii support on PPC and on IRC we gave him some hints to hack up something that works for ppc only and satasii only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA
Here is a patch which does everything The Right Way (TM) and uses proper abstraction for satasii and compiles all x86 specific stuff only on x86.
Huge thanks go to Segher Boessenkool who provided valuable info about all the endianness trickery (especially preprocessor macros) and tested 8 iterations of the code on Linux/PPC.
All programmers except nic3com should be compilable with this new patch. The satasii programmer should work on PowerPC. make distclean make CONFIG_NIC3COM=no Please report any compilation issues to the mailing list. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Index: flashrom-arch_abstraction/hwaccess.c =================================================================== --- flashrom-arch_abstraction/hwaccess.c (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.c (Arbeitskopie) @@ -26,6 +26,8 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,6 +56,22 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; @@ -83,3 +101,33 @@ { return *(volatile uint32_t *) addr; } + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-arch_abstraction/flash.h =================================================================== --- flashrom-arch_abstraction/flash.h (Revision 1008) +++ flashrom-arch_abstraction/flash.h (Arbeitskopie) @@ -63,8 +63,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -407,6 +409,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -603,6 +611,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -610,6 +619,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-arch_abstraction/spi25.c =================================================================== --- flashrom-arch_abstraction/spi25.c (Revision 1008) +++ flashrom-arch_abstraction/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -996,11 +998,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-arch_abstraction/hwaccess.h =================================================================== --- flashrom-arch_abstraction/hwaccess.h (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.h (Arbeitskopie) @@ -24,13 +24,88 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#define ___constant_swab8(x) ((uint8_t)( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#else + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +237,11 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +/* Port I/O is not available on PowerPC. */ + +#else +#error Unknown architecture +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-arch_abstraction/it87spi.c =================================================================== --- flashrom-arch_abstraction/it87spi.c (Revision 1008) +++ flashrom-arch_abstraction/it87spi.c (Arbeitskopie) @@ -23,6 +23,8 @@ * Contains the ITE IT87* SPI specific routines */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include <stdlib.h> #include "flash.h" @@ -351,3 +353,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/physmap.c =================================================================== --- flashrom-arch_abstraction/physmap.c (Revision 1008) +++ flashrom-arch_abstraction/physmap.c (Arbeitskopie) @@ -241,6 +241,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -462,4 +464,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-arch_abstraction/nic3com.c =================================================================== --- flashrom-arch_abstraction/nic3com.c (Revision 1008) +++ flashrom-arch_abstraction/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unknown architecture +#endif Index: flashrom-arch_abstraction/spi.c =================================================================== --- flashrom-arch_abstraction/spi.c (Revision 1008) +++ flashrom-arch_abstraction/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-arch_abstraction/Makefile =================================================================== --- flashrom-arch_abstraction/Makefile (Revision 1008) +++ flashrom-arch_abstraction/Makefile (Arbeitskopie) @@ -124,7 +124,9 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -260,7 +262,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-arch_abstraction/satasii.c =================================================================== --- flashrom-arch_abstraction/satasii.c (Revision 1008) +++ flashrom-arch_abstraction/satasii.c (Arbeitskopie) @@ -62,7 +62,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -82,32 +82,32 @@ { uint32_t ctrl_reg, data_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val; + mmio_le_writel(data_reg, (sii_bar + 4)); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - mmio_writel(ctrl_reg, sii_bar); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; - return (mmio_readl(sii_bar + 4)) & 0xff; + return (mmio_le_readl(sii_bar + 4)) & 0xff; } Index: flashrom-arch_abstraction/wbsio_spi.c =================================================================== --- flashrom-arch_abstraction/wbsio_spi.c (Revision 1008) +++ flashrom-arch_abstraction/wbsio_spi.c (Arbeitskopie) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -199,3 +201,5 @@ return spi_chip_write_1(flash, buf); } + +#endif Index: flashrom-arch_abstraction/chipset_enable.c =================================================================== --- flashrom-arch_abstraction/chipset_enable.c (Revision 1008) +++ flashrom-arch_abstraction/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1425,7 +1430,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-arch_abstraction/sb600spi.c =================================================================== --- flashrom-arch_abstraction/sb600spi.c (Revision 1008) +++ flashrom-arch_abstraction/sb600spi.c (Arbeitskopie) @@ -21,6 +21,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -166,3 +168,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/flashrom.c =================================================================== --- flashrom-arch_abstraction/flashrom.c (Revision 1008) +++ flashrom-arch_abstraction/flashrom.c (Arbeitskopie) @@ -276,6 +276,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -293,6 +294,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { Index: flashrom-arch_abstraction/internal.c =================================================================== --- flashrom-arch_abstraction/internal.c (Revision 1008) +++ flashrom-arch_abstraction/internal.c (Arbeitskopie) @@ -99,10 +99,12 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; int force_boardmismatch = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -112,8 +114,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -166,10 +169,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) { @@ -203,8 +209,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-arch_abstraction/ichspi.c =================================================================== --- flashrom-arch_abstraction/ichspi.c (Revision 1008) +++ flashrom-arch_abstraction/ichspi.c (Arbeitskopie) @@ -33,6 +33,8 @@ * */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -832,3 +834,5 @@ } return ret; } + +#endif Index: flashrom-arch_abstraction/print_wiki.c =================================================================== --- flashrom-arch_abstraction/print_wiki.c (Revision 1008) +++ flashrom-arch_abstraction/print_wiki.c (Arbeitskopie) @@ -104,6 +104,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_url boards_url[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." }, { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, @@ -279,8 +280,10 @@ { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, /* EPIA-N link for now */ { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, @@ -298,18 +301,23 @@ { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, +#endif /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." }, { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo30..." }, +#endif /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", NULL }, { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&..." }, { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, +#endif { NULL, NULL, 0 }, }; @@ -317,6 +325,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_notes boards_notes[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, @@ -324,23 +333,30 @@ { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, { "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." }, { "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" }, +#endif /* Verified working boards that DO need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, +#endif /* Verified working laptops. */ /* None which need comments, yet... */ /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, +#endif { NULL, NULL, 0 }, }; Index: flashrom-arch_abstraction/print.c =================================================================== --- flashrom-arch_abstraction/print.c (Revision 1008) +++ flashrom-arch_abstraction/print.c (Arbeitskopie) @@ -257,6 +257,7 @@ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", }, { "Abit", "Fatal1ty F-I90HD", }, { "Advantech", "PCM-5820", }, @@ -377,13 +378,14 @@ { "VIA", "pc2500e", }, { "VIA", "PC3500G", }, { "VIA", "VB700X", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_bad[] = { /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", }, { "ASRock", "K7VT4A+", }, { "ASUS", "MEW-AM", }, @@ -401,29 +403,31 @@ { "Sun", "Fire x4200", }, { "Sun", "Fire x4540", }, { "Sun", "Fire x4600", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_ok[] = { /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Lenovo", "3000 V100 TF05Cxx", }, { "Acer", "Aspire 1520", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_bad[] = { /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", }, { "ASUS", "Eee PC 701 4G", }, { "Dell", "Latitude CPi A366XT", }, { "HP/Compaq", "nx9010", }, { "IBM/Lenovo", "Thinkpad T40p", }, { "IBM/Lenovo", "240", }, - +#endif {}, }; #endif Index: flashrom-arch_abstraction/board_enable.c =================================================================== --- flashrom-arch_abstraction/board_enable.c (Revision 1008) +++ flashrom-arch_abstraction/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1306,6 +1307,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1349,6 +1352,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1415,7 +1419,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/
On 22.05.2010 23:56, Carl-Daniel Hailfinger wrote:
On 26.03.2010 19:13, Michael Manulis wrote:
I tested the changes on my system. The system is a CurtisWright Raptor board with a single PowerPC 7457 processor. It has a daughter-board from TechnoBox 5575 PCI-over-PMC SATA adapter. The daughter-board has onboard BIOS (AMD flash chip) and EEPROM.
I was able to read, write and erase both chips using satasii programmer.
I did encounter an issue when my rootfs is mounted over NFS. When writing data back onto flash, the data came back in reverse endianness from the original. This was only an issue with NFS-mounted rootfs. When I tested the same procedure with the rootfs mounted from the internal SATA drive, everything was consistent. [...]
vsm:~# ./flashrom -p satasii flashrom v0.9.1-r985 Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0). === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom@flashrom.org if it works for you. Thank you for your help! === Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100. Warning: Flash seems unconnected. Calibrating delay loop... OK. Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000.
Acked-by: Misha Manulis <misha@manulis.com>
On Fri, Mar 26, 2010 at 9:42 AM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006@gmx.net> wrote:
On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote:
Misha Manulis asked for satasii support on PPC and on IRC we gave him some hints to hack up something that works for ppc only and satasii only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA
Here is a patch which does everything The Right Way (TM) and uses proper abstraction for satasii and compiles all x86 specific stuff only on x86.
Huge thanks go to Segher Boessenkool who provided valuable info about all the endianness trickery (especially preprocessor macros) and tested 8 iterations of the code on Linux/PPC.
All programmers except nic3com should be compilable with this new patch. The satasii programmer should work on PowerPC.
make distclean make CONFIG_NIC3COM=no
Please report any issues to the mailing list.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Index: flashrom-arch_abstraction/hwaccess.c =================================================================== --- flashrom-arch_abstraction/hwaccess.c (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.c (Arbeitskopie) @@ -26,6 +26,12 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + +static inline void sync_primitive(void) +{ +} + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,19 +60,43 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +static inline void sync_primitive(void) +{ + asm("eieio" : : : "memory") +} + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; + sync_primitive(); } void mmio_writew(uint16_t val, void *addr) { *(volatile uint16_t *) addr = val; + sync_primitive(); } void mmio_writel(uint32_t val, void *addr) { *(volatile uint32_t *) addr = val; + sync_primitive(); } uint8_t mmio_readb(void *addr) @@ -83,3 +113,33 @@ { return *(volatile uint32_t *) addr; } + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-arch_abstraction/flash.h =================================================================== --- flashrom-arch_abstraction/flash.h (Revision 1008) +++ flashrom-arch_abstraction/flash.h (Arbeitskopie) @@ -63,8 +63,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -407,6 +409,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -603,6 +611,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -610,6 +619,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-arch_abstraction/spi25.c =================================================================== --- flashrom-arch_abstraction/spi25.c (Revision 1008) +++ flashrom-arch_abstraction/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -996,11 +998,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-arch_abstraction/hwaccess.h =================================================================== --- flashrom-arch_abstraction/hwaccess.h (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.h (Arbeitskopie) @@ -24,13 +24,88 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#define ___constant_swab8(x) ((uint8_t)( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#else + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +237,11 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +/* Port I/O is not available on PowerPC. */ + +#else +#error Unknown architecture +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-arch_abstraction/it87spi.c =================================================================== --- flashrom-arch_abstraction/it87spi.c (Revision 1008) +++ flashrom-arch_abstraction/it87spi.c (Arbeitskopie) @@ -23,6 +23,8 @@ * Contains the ITE IT87* SPI specific routines */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include <stdlib.h> #include "flash.h" @@ -351,3 +353,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/physmap.c =================================================================== --- flashrom-arch_abstraction/physmap.c (Revision 1008) +++ flashrom-arch_abstraction/physmap.c (Arbeitskopie) @@ -241,6 +241,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -462,4 +464,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-arch_abstraction/nic3com.c =================================================================== --- flashrom-arch_abstraction/nic3com.c (Revision 1008) +++ flashrom-arch_abstraction/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unknown architecture +#endif Index: flashrom-arch_abstraction/spi.c =================================================================== --- flashrom-arch_abstraction/spi.c (Revision 1008) +++ flashrom-arch_abstraction/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-arch_abstraction/Makefile =================================================================== --- flashrom-arch_abstraction/Makefile (Revision 1008) +++ flashrom-arch_abstraction/Makefile (Arbeitskopie) @@ -124,7 +124,9 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -260,7 +262,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-arch_abstraction/satasii.c =================================================================== --- flashrom-arch_abstraction/satasii.c (Revision 1008) +++ flashrom-arch_abstraction/satasii.c (Arbeitskopie) @@ -62,7 +62,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -82,32 +82,32 @@ { uint32_t ctrl_reg, data_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val; + mmio_le_writel(data_reg, (sii_bar + 4)); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - mmio_writel(ctrl_reg, sii_bar); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; - return (mmio_readl(sii_bar + 4)) & 0xff; + return (mmio_le_readl(sii_bar + 4)) & 0xff; } Index: flashrom-arch_abstraction/wbsio_spi.c =================================================================== --- flashrom-arch_abstraction/wbsio_spi.c (Revision 1008) +++ flashrom-arch_abstraction/wbsio_spi.c (Arbeitskopie) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -199,3 +201,5 @@ return spi_chip_write_1(flash, buf); } + +#endif Index: flashrom-arch_abstraction/chipset_enable.c =================================================================== --- flashrom-arch_abstraction/chipset_enable.c (Revision 1008) +++ flashrom-arch_abstraction/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1425,7 +1430,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-arch_abstraction/sb600spi.c =================================================================== --- flashrom-arch_abstraction/sb600spi.c (Revision 1008) +++ flashrom-arch_abstraction/sb600spi.c (Arbeitskopie) @@ -21,6 +21,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -166,3 +168,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/flashrom.c =================================================================== --- flashrom-arch_abstraction/flashrom.c (Revision 1008) +++ flashrom-arch_abstraction/flashrom.c (Arbeitskopie) @@ -276,6 +276,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -293,6 +294,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { Index: flashrom-arch_abstraction/internal.c =================================================================== --- flashrom-arch_abstraction/internal.c (Revision 1008) +++ flashrom-arch_abstraction/internal.c (Arbeitskopie) @@ -99,10 +99,12 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; int force_boardmismatch = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -112,8 +114,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -166,10 +169,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) { @@ -203,8 +209,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-arch_abstraction/ichspi.c =================================================================== --- flashrom-arch_abstraction/ichspi.c (Revision 1008) +++ flashrom-arch_abstraction/ichspi.c (Arbeitskopie) @@ -33,6 +33,8 @@ * */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -832,3 +834,5 @@ } return ret; } + +#endif Index: flashrom-arch_abstraction/print_wiki.c =================================================================== --- flashrom-arch_abstraction/print_wiki.c (Revision 1008) +++ flashrom-arch_abstraction/print_wiki.c (Arbeitskopie) @@ -104,6 +104,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_url boards_url[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." }, { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, @@ -279,8 +280,10 @@ { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, /* EPIA-N link for now */ { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, @@ -298,18 +301,23 @@ { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, +#endif /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." }, { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo30..." }, +#endif /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", NULL }, { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&..." }, { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, +#endif { NULL, NULL, 0 }, }; @@ -317,6 +325,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_notes boards_notes[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, @@ -324,23 +333,30 @@ { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, { "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." }, { "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" }, +#endif /* Verified working boards that DO need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, +#endif /* Verified working laptops. */ /* None which need comments, yet... */ /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, +#endif { NULL, NULL, 0 }, }; Index: flashrom-arch_abstraction/print.c =================================================================== --- flashrom-arch_abstraction/print.c (Revision 1008) +++ flashrom-arch_abstraction/print.c (Arbeitskopie) @@ -257,6 +257,7 @@ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", }, { "Abit", "Fatal1ty F-I90HD", }, { "Advantech", "PCM-5820", }, @@ -377,13 +378,14 @@ { "VIA", "pc2500e", }, { "VIA", "PC3500G", }, { "VIA", "VB700X", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_bad[] = { /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", }, { "ASRock", "K7VT4A+", }, { "ASUS", "MEW-AM", }, @@ -401,29 +403,31 @@ { "Sun", "Fire x4200", }, { "Sun", "Fire x4540", }, { "Sun", "Fire x4600", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_ok[] = { /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Lenovo", "3000 V100 TF05Cxx", }, { "Acer", "Aspire 1520", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_bad[] = { /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", }, { "ASUS", "Eee PC 701 4G", }, { "Dell", "Latitude CPi A366XT", }, { "HP/Compaq", "nx9010", }, { "IBM/Lenovo", "Thinkpad T40p", }, { "IBM/Lenovo", "240", }, - +#endif {}, }; #endif Index: flashrom-arch_abstraction/board_enable.c =================================================================== --- flashrom-arch_abstraction/board_enable.c (Revision 1008) +++ flashrom-arch_abstraction/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1306,6 +1307,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1349,6 +1352,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1415,7 +1419,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/
New patch. Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com which requires x86 for now. To compile without nic3com, run make distclean make CONFIG_NIC3COM=no Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Index: flashrom-arch_abstraction/hwaccess.c =================================================================== --- flashrom-arch_abstraction/hwaccess.c (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.c (Arbeitskopie) @@ -26,6 +26,12 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + +static inline void sync_primitive(void) +{ +} + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,19 +60,58 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +static inline void sync_primitive(void) +{ + asm("eieio" : : : "memory") +} + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* Not sure about the sync primitive. */ +static inline void sync_primitive(void) +{ +} + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; + sync_primitive(); } void mmio_writew(uint16_t val, void *addr) { *(volatile uint16_t *) addr = val; + sync_primitive(); } void mmio_writel(uint32_t val, void *addr) { *(volatile uint32_t *) addr = val; + sync_primitive(); } uint8_t mmio_readb(void *addr) @@ -83,3 +128,33 @@ { return *(volatile uint32_t *) addr; } + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-arch_abstraction/flash.h =================================================================== --- flashrom-arch_abstraction/flash.h (Revision 1008) +++ flashrom-arch_abstraction/flash.h (Arbeitskopie) @@ -63,8 +63,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -407,6 +409,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -603,6 +611,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -610,6 +619,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-arch_abstraction/spi25.c =================================================================== --- flashrom-arch_abstraction/spi25.c (Revision 1008) +++ flashrom-arch_abstraction/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -996,11 +998,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-arch_abstraction/hwaccess.h =================================================================== --- flashrom-arch_abstraction/hwaccess.h (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.h (Arbeitskopie) @@ -24,13 +24,137 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#if defined (__i386__) || defined (__x86_64__) + +/* All x86 is little-endian. */ +#define __FLASHROM_LITTLE_ENDIAN__ 1 + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* MIPS can be either endian. */ +#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL) +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB) +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif + +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PowerPC can be either endian. */ +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) +#define __FLASHROM_BIG_ENDIAN__ 1 +/* Error checking in case some weird header has #defines for LE as well. */ +#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__) +#error Conflicting endianness #define +#endif +#else +#error Little-endian PowerPC #defines are unknown +#endif + +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +/* Nonstandard libc-specific macros for determining endianness. */ +#if defined(__GLIBC__) +#include <endian.h> +#if BYTE_ORDER == LITTLE_ENDIAN +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif BYTE_ORDER == BIG_ENDIAN +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif +#endif +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +#error Can not determine endianness. Please add support for your arch or libc. +#endif + +#define ___constant_swab8(x) ((uint8_t)( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (__FLASHROM_BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#elif defined (__FLASHROM_LITTLE_ENDIAN__) + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#else + +#error Could not determine endianness. + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +286,18 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* Port I/O is not available on PowerPC. */ + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* Port I/O is not available on MIPS. */ + +#else + +#error Unknown architecture, please check if it supports port IO. + +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-arch_abstraction/it87spi.c =================================================================== --- flashrom-arch_abstraction/it87spi.c (Revision 1008) +++ flashrom-arch_abstraction/it87spi.c (Arbeitskopie) @@ -23,6 +23,8 @@ * Contains the ITE IT87* SPI specific routines */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include <stdlib.h> #include "flash.h" @@ -351,3 +353,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/physmap.c =================================================================== --- flashrom-arch_abstraction/physmap.c (Revision 1008) +++ flashrom-arch_abstraction/physmap.c (Arbeitskopie) @@ -241,6 +241,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -462,4 +464,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-arch_abstraction/spi.c =================================================================== --- flashrom-arch_abstraction/spi.c (Revision 1008) +++ flashrom-arch_abstraction/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-arch_abstraction/nic3com.c =================================================================== --- flashrom-arch_abstraction/nic3com.c (Revision 1008) +++ flashrom-arch_abstraction/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unsupported architecture for nic3com. You need a way to emulate port IO access. +#endif Index: flashrom-arch_abstraction/Makefile =================================================================== --- flashrom-arch_abstraction/Makefile (Revision 1008) +++ flashrom-arch_abstraction/Makefile (Arbeitskopie) @@ -124,7 +124,9 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -260,7 +262,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-arch_abstraction/wbsio_spi.c =================================================================== --- flashrom-arch_abstraction/wbsio_spi.c (Revision 1008) +++ flashrom-arch_abstraction/wbsio_spi.c (Arbeitskopie) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -199,3 +201,5 @@ return spi_chip_write_1(flash, buf); } + +#endif Index: flashrom-arch_abstraction/chipset_enable.c =================================================================== --- flashrom-arch_abstraction/chipset_enable.c (Revision 1008) +++ flashrom-arch_abstraction/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1425,7 +1430,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-arch_abstraction/sb600spi.c =================================================================== --- flashrom-arch_abstraction/sb600spi.c (Revision 1008) +++ flashrom-arch_abstraction/sb600spi.c (Arbeitskopie) @@ -21,6 +21,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -166,3 +168,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/flashrom.c =================================================================== --- flashrom-arch_abstraction/flashrom.c (Revision 1008) +++ flashrom-arch_abstraction/flashrom.c (Arbeitskopie) @@ -276,6 +276,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -293,6 +294,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { Index: flashrom-arch_abstraction/internal.c =================================================================== --- flashrom-arch_abstraction/internal.c (Revision 1008) +++ flashrom-arch_abstraction/internal.c (Arbeitskopie) @@ -99,10 +99,12 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; int force_boardmismatch = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -112,8 +114,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -166,10 +169,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) { @@ -203,8 +209,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-arch_abstraction/ichspi.c =================================================================== --- flashrom-arch_abstraction/ichspi.c (Revision 1008) +++ flashrom-arch_abstraction/ichspi.c (Arbeitskopie) @@ -33,6 +33,8 @@ * */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -832,3 +834,5 @@ } return ret; } + +#endif Index: flashrom-arch_abstraction/print_wiki.c =================================================================== --- flashrom-arch_abstraction/print_wiki.c (Revision 1008) +++ flashrom-arch_abstraction/print_wiki.c (Arbeitskopie) @@ -104,6 +104,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_url boards_url[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." }, { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, @@ -279,8 +280,10 @@ { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, /* EPIA-N link for now */ { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, @@ -298,18 +301,23 @@ { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, +#endif /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." }, { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo30..." }, +#endif /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", NULL }, { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&..." }, { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, +#endif { NULL, NULL, 0 }, }; @@ -317,6 +325,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_notes boards_notes[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, @@ -324,23 +333,30 @@ { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, { "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." }, { "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" }, +#endif /* Verified working boards that DO need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, +#endif /* Verified working laptops. */ /* None which need comments, yet... */ /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, +#endif { NULL, NULL, 0 }, }; Index: flashrom-arch_abstraction/print.c =================================================================== --- flashrom-arch_abstraction/print.c (Revision 1008) +++ flashrom-arch_abstraction/print.c (Arbeitskopie) @@ -257,6 +257,7 @@ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", }, { "Abit", "Fatal1ty F-I90HD", }, { "Advantech", "PCM-5820", }, @@ -377,13 +378,14 @@ { "VIA", "pc2500e", }, { "VIA", "PC3500G", }, { "VIA", "VB700X", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_bad[] = { /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", }, { "ASRock", "K7VT4A+", }, { "ASUS", "MEW-AM", }, @@ -401,29 +403,31 @@ { "Sun", "Fire x4200", }, { "Sun", "Fire x4540", }, { "Sun", "Fire x4600", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_ok[] = { /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Lenovo", "3000 V100 TF05Cxx", }, { "Acer", "Aspire 1520", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_bad[] = { /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", }, { "ASUS", "Eee PC 701 4G", }, { "Dell", "Latitude CPi A366XT", }, { "HP/Compaq", "nx9010", }, { "IBM/Lenovo", "Thinkpad T40p", }, { "IBM/Lenovo", "240", }, - +#endif {}, }; #endif Index: flashrom-arch_abstraction/board_enable.c =================================================================== --- flashrom-arch_abstraction/board_enable.c (Revision 1008) +++ flashrom-arch_abstraction/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1306,6 +1307,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1349,6 +1352,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1415,7 +1419,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/
Segher: I'd appreciate if you could take a look and ack it if this looks OK from a PowerPC perspective. Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Index: flashrom-arch_abstraction/hwaccess.c =================================================================== --- flashrom-arch_abstraction/hwaccess.c (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.c (Arbeitskopie) @@ -26,6 +26,12 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + +static inline void sync_primitive(void) +{ +} + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,19 +60,62 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +static inline void sync_primitive(void) +{ + asm("eieio" : : : "memory") +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void release_io_perms(void) +{ +} + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* Not sure about the sync primitive. */ +static inline void sync_primitive(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; + sync_primitive(); } void mmio_writew(uint16_t val, void *addr) { *(volatile uint16_t *) addr = val; + sync_primitive(); } void mmio_writel(uint32_t val, void *addr) { *(volatile uint32_t *) addr = val; + sync_primitive(); } uint8_t mmio_readb(void *addr) @@ -83,3 +132,33 @@ { return *(volatile uint32_t *) addr; } + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-arch_abstraction/flash.h =================================================================== --- flashrom-arch_abstraction/flash.h (Revision 1008) +++ flashrom-arch_abstraction/flash.h (Arbeitskopie) @@ -63,8 +63,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -407,6 +409,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -603,6 +611,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -610,6 +619,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-arch_abstraction/spi25.c =================================================================== --- flashrom-arch_abstraction/spi25.c (Revision 1008) +++ flashrom-arch_abstraction/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -996,11 +998,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-arch_abstraction/hwaccess.h =================================================================== --- flashrom-arch_abstraction/hwaccess.h (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.h (Arbeitskopie) @@ -24,13 +24,137 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#if defined (__i386__) || defined (__x86_64__) + +/* All x86 is little-endian. */ +#define __FLASHROM_LITTLE_ENDIAN__ 1 + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* MIPS can be either endian. */ +#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL) +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB) +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif + +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PowerPC can be either endian. */ +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) +#define __FLASHROM_BIG_ENDIAN__ 1 +/* Error checking in case some weird header has #defines for LE as well. */ +#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__) +#error Conflicting endianness #define +#endif +#else +#error Little-endian PowerPC #defines are unknown +#endif + +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +/* Nonstandard libc-specific macros for determining endianness. */ +#if defined(__GLIBC__) +#include <endian.h> +#if BYTE_ORDER == LITTLE_ENDIAN +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif BYTE_ORDER == BIG_ENDIAN +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif +#endif +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +#error Unable to determine endianness. Please add support for your arch or libc. +#endif + +#define ___constant_swab8(x) ((uint8_t)( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (__FLASHROM_BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#elif defined (__FLASHROM_LITTLE_ENDIAN__) + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#else + +#error Could not determine endianness. + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +286,18 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PCI port I/O is not yet implemented on PowerPC. */ + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* PCI port I/O is not yet implemented on MIPS. */ + +#else + +#error Unknown architecture, please check if it supports PCI port IO. + +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-arch_abstraction/it87spi.c =================================================================== --- flashrom-arch_abstraction/it87spi.c (Revision 1008) +++ flashrom-arch_abstraction/it87spi.c (Arbeitskopie) @@ -23,6 +23,8 @@ * Contains the ITE IT87* SPI specific routines */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include <stdlib.h> #include "flash.h" @@ -351,3 +353,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/physmap.c =================================================================== --- flashrom-arch_abstraction/physmap.c (Revision 1008) +++ flashrom-arch_abstraction/physmap.c (Arbeitskopie) @@ -241,6 +241,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -462,4 +464,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-arch_abstraction/spi.c =================================================================== --- flashrom-arch_abstraction/spi.c (Revision 1008) +++ flashrom-arch_abstraction/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-arch_abstraction/nic3com.c =================================================================== --- flashrom-arch_abstraction/nic3com.c (Revision 1008) +++ flashrom-arch_abstraction/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unsupported architecture for nic3com. You need a way to emulate port IO access. +#endif Index: flashrom-arch_abstraction/Makefile =================================================================== --- flashrom-arch_abstraction/Makefile (Revision 1008) +++ flashrom-arch_abstraction/Makefile (Arbeitskopie) @@ -124,7 +124,9 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -260,7 +262,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-arch_abstraction/wbsio_spi.c =================================================================== --- flashrom-arch_abstraction/wbsio_spi.c (Revision 1008) +++ flashrom-arch_abstraction/wbsio_spi.c (Arbeitskopie) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -199,3 +201,5 @@ return spi_chip_write_1(flash, buf); } + +#endif Index: flashrom-arch_abstraction/chipset_enable.c =================================================================== --- flashrom-arch_abstraction/chipset_enable.c (Revision 1008) +++ flashrom-arch_abstraction/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1425,7 +1430,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-arch_abstraction/sb600spi.c =================================================================== --- flashrom-arch_abstraction/sb600spi.c (Revision 1008) +++ flashrom-arch_abstraction/sb600spi.c (Arbeitskopie) @@ -21,6 +21,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -166,3 +168,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/flashrom.c =================================================================== --- flashrom-arch_abstraction/flashrom.c (Revision 1008) +++ flashrom-arch_abstraction/flashrom.c (Arbeitskopie) @@ -276,6 +276,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -293,6 +294,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { @@ -1208,17 +1210,22 @@ #endif #endif #ifdef __clang__ - msg_ginfo(" LLVM %i/clang %i", __llvm__, __clang__); + msg_ginfo(" LLVM %i/clang %i, ", __llvm__, __clang__); #elif defined(__GNUC__) msg_ginfo(" GCC"); #ifdef __VERSION__ - msg_ginfo(" %s", __VERSION__); + msg_ginfo(" %s,", __VERSION__); #else - msg_ginfo(" unknown version"); + msg_ginfo(" unknown version,"); #endif #else - msg_ginfo(" unknown compiler"); + msg_ginfo(" unknown compiler,"); #endif +#if defined (__FLASHROM_LITTLE_ENDIAN__) + msg_ginfo(" little endian"); +#else + msg_ginfo(" big endian"); +#endif msg_ginfo("\n"); } Index: flashrom-arch_abstraction/internal.c =================================================================== --- flashrom-arch_abstraction/internal.c (Revision 1008) +++ flashrom-arch_abstraction/internal.c (Arbeitskopie) @@ -99,10 +99,12 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; int force_boardmismatch = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -112,8 +114,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -166,10 +169,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) { @@ -203,8 +209,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-arch_abstraction/ichspi.c =================================================================== --- flashrom-arch_abstraction/ichspi.c (Revision 1008) +++ flashrom-arch_abstraction/ichspi.c (Arbeitskopie) @@ -33,6 +33,8 @@ * */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -832,3 +834,5 @@ } return ret; } + +#endif Index: flashrom-arch_abstraction/print_wiki.c =================================================================== --- flashrom-arch_abstraction/print_wiki.c (Revision 1008) +++ flashrom-arch_abstraction/print_wiki.c (Arbeitskopie) @@ -104,6 +104,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_url boards_url[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." }, { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, @@ -279,8 +280,10 @@ { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, /* EPIA-N link for now */ { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, @@ -298,18 +301,23 @@ { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, +#endif /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." }, { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo30..." }, +#endif /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", NULL }, { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&..." }, { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, +#endif { NULL, NULL, 0 }, }; @@ -317,6 +325,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_notes boards_notes[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, @@ -324,23 +333,30 @@ { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, { "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." }, { "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" }, +#endif /* Verified working boards that DO need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, +#endif /* Verified working laptops. */ /* None which need comments, yet... */ /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, +#endif { NULL, NULL, 0 }, }; Index: flashrom-arch_abstraction/print.c =================================================================== --- flashrom-arch_abstraction/print.c (Revision 1008) +++ flashrom-arch_abstraction/print.c (Arbeitskopie) @@ -257,6 +257,7 @@ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", }, { "Abit", "Fatal1ty F-I90HD", }, { "Advantech", "PCM-5820", }, @@ -377,13 +378,14 @@ { "VIA", "pc2500e", }, { "VIA", "PC3500G", }, { "VIA", "VB700X", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_bad[] = { /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", }, { "ASRock", "K7VT4A+", }, { "ASUS", "MEW-AM", }, @@ -401,29 +403,31 @@ { "Sun", "Fire x4200", }, { "Sun", "Fire x4540", }, { "Sun", "Fire x4600", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_ok[] = { /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Lenovo", "3000 V100 TF05Cxx", }, { "Acer", "Aspire 1520", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_bad[] = { /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", }, { "ASUS", "Eee PC 701 4G", }, { "Dell", "Latitude CPi A366XT", }, { "HP/Compaq", "nx9010", }, { "IBM/Lenovo", "Thinkpad T40p", }, { "IBM/Lenovo", "240", }, - +#endif {}, }; #endif Index: flashrom-arch_abstraction/board_enable.c =================================================================== --- flashrom-arch_abstraction/board_enable.c (Revision 1008) +++ flashrom-arch_abstraction/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1306,6 +1307,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1349,6 +1352,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1415,7 +1419,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/
Carl-Daniel Hailfinger wrote:
Segher: I'd appreciate if you could take a look and ack it if this looks OK from a PowerPC perspective.
Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian)
No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them.
Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now.
To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This patch together with setting flash_base to 0x1fc00000 worked fine on my yeeloong LM8089 (8.9" version, mipsel (little-endian) ). I attach the logs of -Vr, -V and -w together with lspci. Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> -- Regards Vladimir 'φ-coder/phcoder' Serbinenko flashrom v0.9.2-r1011 on Linux 2.6.34-libre-lemote (mips64), built with libpci 3.0.0, GCC 4.3.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... 252M loops per second, 10 myus = 12 us, 100 myus = 97 us, 1000 myus = 950 us, 10000 myus = 9774 us, OK. Initializing internal programmer No coreboot table found. This chipset supports the following protocols: Non-SPI. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xf7, id2 0x11 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xf7, id2 0x11 Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Intel 28F004S5, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004BV/BE-B, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004BV/BE-T, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/CV/CE-B, 512 KB: probe_82802ab: id1 0xf7, id2 0x11, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/CV/CE-T, 512 KB: probe_82802ab: id1 0xf7, id2 0x11, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Found chip "SST SST39VF040" (512 KB, Parallel) at physical address 0x1fc00000. Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xf7, id2 0x11 Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for EON unknown EON SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. flashrom v0.9.2-r1011 on Linux 2.6.34-libre-lemote (mips64), built with libpci 3.0.0, GCC 4.3.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... 262M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 988 us, 10000 myus = 10150 us, OK. Initializing internal programmer No coreboot table found. This chipset supports the following protocols: Non-SPI. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xf7, id2 0x11 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xf7, id2 0x11 Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Intel 28F004S5, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004BV/BE-B, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004BV/BE-T, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/CV/CE-B, 512 KB: probe_82802ab: id1 0xf7, id2 0x11, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/CV/CE-T, 512 KB: probe_82802ab: id1 0xf7, id2 0x11, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Found chip "SST SST39VF040" (512 KB, Parallel) at physical address 0x1fc00000. Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xf7, id2 0x11 Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0xf7, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xd7 Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for EON unknown EON SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === Reading flash... done. flashrom v0.9.2-r1011 on Linux 2.6.34-libre-lemote (mips64), built with libpci 3.0.0, GCC 4.3.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. This chipset supports the following protocols: Non-SPI. WARNING: No chipset found. Flash detection will most likely fail. Found chip "SST SST39VF040" (512 KB, Parallel) at physical address 0x1fc00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... SUCCESS. Programming page: DONE!ss: 0x0007f000 COMPLETE. Verifying flash... VERIFIED. 00:07.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10) Subsystem: Realtek Semiconductor Co., Ltd. RT8139 [10ec:8139] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 37 Region 0: I/O ports at 4000 [size=256] Region 1: Memory at 41023000 (32-bit, non-prefetchable) [size=256] Expansion ROM at 41000000 [size=128K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: 8139too 00: ec 10 39 81 47 01 90 02 10 00 00 02 00 40 00 00 10: 01 40 00 00 00 30 02 41 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81 30: 01 00 00 41 50 00 00 00 00 00 00 00 25 01 20 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 02 76 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:08.0 VGA compatible controller [0300]: Silicon Motion, Inc. SM712 LynxEM+ [126f:0712] (rev b0) (prog-if 00 [VGA controller]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Interrupt: pin A routed to IRQ 38 Region 0: Memory at 40000000 (32-bit, non-prefetchable) [size=16M] Capabilities: [40] Power Management version 1 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: smtcfb 00: 6f 12 12 07 07 00 30 02 b0 00 00 03 00 40 00 00 10: 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 26 01 00 00 40: 01 00 01 06 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 44) (prog-if 10 [OHCI]) Subsystem: NEC Corporation Hama USB 2.0 CardBus [1033:0035] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (250ns min, 10500ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 39 Region 0: Memory at 41020000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ Kernel driver in use: ohci_hcd 00: 33 10 35 00 46 01 10 02 44 10 03 0c 08 40 80 00 10: 00 00 02 41 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 33 10 35 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 27 01 01 2a 40: 01 00 02 7e 00 80 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 1e 33 14 01 42 6c 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.1 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 05) (prog-if 20 [EHCI]) Subsystem: NEC Corporation USB 2.0 [1033:00e0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (4000ns min, 8500ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 39 Region 0: Memory at 41023100 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd 00: 33 10 e0 00 56 01 10 02 05 20 03 0c 08 40 00 00 10: 00 31 02 41 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 33 10 e0 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 27 01 10 22 40: 01 00 02 7e 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 3f 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 1e 33 14 01 42 6c 00 00 01 00 00 00 00 00 08 c0 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0e.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: I/O ports at 4c70 [size=8] Region 1: I/O ports at 4400 [size=256] Region 2: I/O ports at 4c00 [size=64] Region 4: I/O ports at 4800 [size=128] Region 5: I/O ports at 4c40 [size=32] Kernel modules: cs5535-gpio 00: 22 10 90 20 01 00 00 00 03 00 01 06 08 40 80 00 10: 71 4c 00 00 01 44 00 00 01 4c 00 00 00 00 00 00 20: 01 48 00 00 41 4c 00 00 00 00 00 00 22 10 90 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 01 00 00 00 0d 00 00 80 00 4c 00 00 01 f0 00 00 00:0e.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01) (prog-if 80 [Master]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (16000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 14 Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] Region 4: I/O ports at 4c60 [size=16] Kernel driver in use: AMD_IDE 00: 22 10 9a 20 05 00 00 00 01 80 01 01 08 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 61 4c 00 00 00 00 00 00 00 00 00 00 22 10 9a 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 0e 01 00 40 40: 02 f0 00 00 00 00 00 00 00 00 98 20 20 00 00 20 50: 03 03 03 c6 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0e.3 Multimedia audio controller [0401]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio [1022:2093] (rev 01) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio [1022:2093] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (16000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 9 Region 0: I/O ports at 4880 [size=128] Kernel driver in use: cs5535audio Kernel modules: snd-cs5535audio 00: 22 10 93 20 05 00 00 00 01 00 01 04 08 00 00 00 10: 81 48 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 93 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 09 01 00 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0e.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02) (prog-if 10 [OHCI]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (16000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: Memory at 41021000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 22 10 94 20 06 00 00 00 02 10 03 0c 08 00 00 00 10: 00 10 02 41 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 94 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 0b 09 00 00 00 00 00 00:0e.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02) (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (16000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: Memory at 41022000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ehci_hcd 00: 22 10 95 20 06 00 00 00 02 20 03 0c 08 00 00 00 10: 00 20 02 41 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 95 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 60: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 20 02 41 06 20 00 08
On 25.05.2010 04:00, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
Carl-Daniel Hailfinger wrote:
Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This patch together with setting flash_base to 0x1fc00000 worked fine on my yeeloong LM8089 (8.9" version, mipsel (little-endian) ). I attach the logs of -Vr, -V and -w together with lspci.
Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com>
Thanks for the review and thanks for testing. Is there a way to determine the chipset and/or the board from userspace? We'll need that to set buses_supported and flash_base correctly. Regards, Carl-Daniel -- http://www.hailfinger.org/
Carl-Daniel Hailfinger wrote:
On 25.05.2010 04:00, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
Carl-Daniel Hailfinger wrote:
Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This patch together with setting flash_base to 0x1fc00000 worked fine on my yeeloong LM8089 (8.9" version, mipsel (little-endian) ). I attach the logs of -Vr, -V and -w together with lspci.
Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com>
Thanks for the review and thanks for testing.
Is there a way to determine the chipset and/or the board from userspace?
I don't think it's actualy necessary. The PCI and LIO bus interfaces as well as address BootROM is mapped to is part of Loongson 2F (CPU) specification. So it's enough to check CPU model. But if you want to be on a safe side you can check "system type" in /proc/cpuinfo as well.
We'll need that to set buses_supported and flash_base correctly.
Regards, Carl-Daniel
-- Regards Vladimir 'φ-coder/phcoder' Serbinenko system type : lemote-yeeloong-2f-8.9inches processor : 0 cpu model : ICT Loongson-2 V0.3 FPU V0.1 BogoMIPS : 528.38 wait instruction : yes microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] ASEs implemented : shadow register sets : 1 core : 0 VCED exceptions : not available VCEI exceptions : not available
Segher: I'd appreciate if you could take a look and ack it if this looks OK from a PowerPC perspective. New patch. Fix compilation on PowerPC. Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH! Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Index: flashrom-arch_abstraction/hwaccess.c =================================================================== --- flashrom-arch_abstraction/hwaccess.c (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.c (Arbeitskopie) @@ -26,6 +26,12 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + +static inline void sync_primitive(void) +{ +} + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,19 +60,62 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +static inline void sync_primitive(void) +{ + asm("eieio" : : : "memory"); +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void release_io_perms(void) +{ +} + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* Not sure about the sync primitive. */ +static inline void sync_primitive(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; + sync_primitive(); } void mmio_writew(uint16_t val, void *addr) { *(volatile uint16_t *) addr = val; + sync_primitive(); } void mmio_writel(uint32_t val, void *addr) { *(volatile uint32_t *) addr = val; + sync_primitive(); } uint8_t mmio_readb(void *addr) @@ -83,3 +132,33 @@ { return *(volatile uint32_t *) addr; } + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-arch_abstraction/flash.h =================================================================== --- flashrom-arch_abstraction/flash.h (Revision 1008) +++ flashrom-arch_abstraction/flash.h (Arbeitskopie) @@ -63,8 +63,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -407,6 +409,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -603,6 +611,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -610,6 +619,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-arch_abstraction/spi25.c =================================================================== --- flashrom-arch_abstraction/spi25.c (Revision 1008) +++ flashrom-arch_abstraction/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -996,11 +998,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-arch_abstraction/hwaccess.h =================================================================== --- flashrom-arch_abstraction/hwaccess.h (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.h (Arbeitskopie) @@ -24,13 +24,137 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#if defined (__i386__) || defined (__x86_64__) + +/* All x86 is little-endian. */ +#define __FLASHROM_LITTLE_ENDIAN__ 1 + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* MIPS can be either endian. */ +#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL) +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB) +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif + +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PowerPC can be either endian. */ +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) +#define __FLASHROM_BIG_ENDIAN__ 1 +/* Error checking in case some weird header has #defines for LE as well. */ +#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__) +#error Conflicting endianness #define +#endif +#else +#error Little-endian PowerPC #defines are unknown +#endif + +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +/* Nonstandard libc-specific macros for determining endianness. */ +#if defined(__GLIBC__) +#include <endian.h> +#if BYTE_ORDER == LITTLE_ENDIAN +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif BYTE_ORDER == BIG_ENDIAN +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif +#endif +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +#error Unable to determine endianness. Please add support for your arch or libc. +#endif + +#define ___constant_swab8(x) ((uint8_t)( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (__FLASHROM_BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#elif defined (__FLASHROM_LITTLE_ENDIAN__) + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#else + +#error Could not determine endianness. + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +286,18 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PCI port I/O is not yet implemented on PowerPC. */ + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* PCI port I/O is not yet implemented on MIPS. */ + +#else + +#error Unknown architecture, please check if it supports PCI port IO. + +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-arch_abstraction/it87spi.c =================================================================== --- flashrom-arch_abstraction/it87spi.c (Revision 1008) +++ flashrom-arch_abstraction/it87spi.c (Arbeitskopie) @@ -23,6 +23,8 @@ * Contains the ITE IT87* SPI specific routines */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include <stdlib.h> #include "flash.h" @@ -351,3 +353,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/physmap.c =================================================================== --- flashrom-arch_abstraction/physmap.c (Revision 1008) +++ flashrom-arch_abstraction/physmap.c (Arbeitskopie) @@ -241,6 +241,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -462,4 +464,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-arch_abstraction/spi.c =================================================================== --- flashrom-arch_abstraction/spi.c (Revision 1008) +++ flashrom-arch_abstraction/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-arch_abstraction/nic3com.c =================================================================== --- flashrom-arch_abstraction/nic3com.c (Revision 1008) +++ flashrom-arch_abstraction/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unsupported architecture for nic3com. You need a way to emulate port IO access. +#endif Index: flashrom-arch_abstraction/Makefile =================================================================== --- flashrom-arch_abstraction/Makefile (Revision 1008) +++ flashrom-arch_abstraction/Makefile (Arbeitskopie) @@ -124,7 +124,9 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -260,7 +262,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-arch_abstraction/wbsio_spi.c =================================================================== --- flashrom-arch_abstraction/wbsio_spi.c (Revision 1008) +++ flashrom-arch_abstraction/wbsio_spi.c (Arbeitskopie) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -199,3 +201,5 @@ return spi_chip_write_1(flash, buf); } + +#endif Index: flashrom-arch_abstraction/chipset_enable.c =================================================================== --- flashrom-arch_abstraction/chipset_enable.c (Revision 1008) +++ flashrom-arch_abstraction/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1425,7 +1430,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-arch_abstraction/sb600spi.c =================================================================== --- flashrom-arch_abstraction/sb600spi.c (Revision 1008) +++ flashrom-arch_abstraction/sb600spi.c (Arbeitskopie) @@ -21,6 +21,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -166,3 +168,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/flashrom.c =================================================================== --- flashrom-arch_abstraction/flashrom.c (Revision 1008) +++ flashrom-arch_abstraction/flashrom.c (Arbeitskopie) @@ -276,6 +276,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -293,6 +294,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { @@ -1208,17 +1210,22 @@ #endif #endif #ifdef __clang__ - msg_ginfo(" LLVM %i/clang %i", __llvm__, __clang__); + msg_ginfo(" LLVM %i/clang %i, ", __llvm__, __clang__); #elif defined(__GNUC__) msg_ginfo(" GCC"); #ifdef __VERSION__ - msg_ginfo(" %s", __VERSION__); + msg_ginfo(" %s,", __VERSION__); #else - msg_ginfo(" unknown version"); + msg_ginfo(" unknown version,"); #endif #else - msg_ginfo(" unknown compiler"); + msg_ginfo(" unknown compiler,"); #endif +#if defined (__FLASHROM_LITTLE_ENDIAN__) + msg_ginfo(" little endian"); +#else + msg_ginfo(" big endian"); +#endif msg_ginfo("\n"); } Index: flashrom-arch_abstraction/internal.c =================================================================== --- flashrom-arch_abstraction/internal.c (Revision 1008) +++ flashrom-arch_abstraction/internal.c (Arbeitskopie) @@ -99,10 +99,12 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; int force_boardmismatch = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -112,8 +114,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -166,10 +169,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) { @@ -203,8 +209,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-arch_abstraction/ichspi.c =================================================================== --- flashrom-arch_abstraction/ichspi.c (Revision 1008) +++ flashrom-arch_abstraction/ichspi.c (Arbeitskopie) @@ -33,6 +33,8 @@ * */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -832,3 +834,5 @@ } return ret; } + +#endif Index: flashrom-arch_abstraction/print_wiki.c =================================================================== --- flashrom-arch_abstraction/print_wiki.c (Revision 1008) +++ flashrom-arch_abstraction/print_wiki.c (Arbeitskopie) @@ -104,6 +104,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_url boards_url[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." }, { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, @@ -279,8 +280,10 @@ { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, /* EPIA-N link for now */ { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, @@ -298,18 +301,23 @@ { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, +#endif /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." }, { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo30..." }, +#endif /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", NULL }, { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&..." }, { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, +#endif { NULL, NULL, 0 }, }; @@ -317,6 +325,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_notes boards_notes[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, @@ -324,23 +333,30 @@ { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, { "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." }, { "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" }, +#endif /* Verified working boards that DO need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, +#endif /* Verified working laptops. */ /* None which need comments, yet... */ /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, +#endif { NULL, NULL, 0 }, }; Index: flashrom-arch_abstraction/print.c =================================================================== --- flashrom-arch_abstraction/print.c (Revision 1008) +++ flashrom-arch_abstraction/print.c (Arbeitskopie) @@ -257,6 +257,7 @@ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", }, { "Abit", "Fatal1ty F-I90HD", }, { "Advantech", "PCM-5820", }, @@ -377,13 +378,14 @@ { "VIA", "pc2500e", }, { "VIA", "PC3500G", }, { "VIA", "VB700X", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_bad[] = { /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", }, { "ASRock", "K7VT4A+", }, { "ASUS", "MEW-AM", }, @@ -401,29 +403,31 @@ { "Sun", "Fire x4200", }, { "Sun", "Fire x4540", }, { "Sun", "Fire x4600", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_ok[] = { /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Lenovo", "3000 V100 TF05Cxx", }, { "Acer", "Aspire 1520", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_bad[] = { /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", }, { "ASUS", "Eee PC 701 4G", }, { "Dell", "Latitude CPi A366XT", }, { "HP/Compaq", "nx9010", }, { "IBM/Lenovo", "Thinkpad T40p", }, { "IBM/Lenovo", "240", }, - +#endif {}, }; #endif Index: flashrom-arch_abstraction/board_enable.c =================================================================== --- flashrom-arch_abstraction/board_enable.c (Revision 1008) +++ flashrom-arch_abstraction/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1306,6 +1307,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1349,6 +1352,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1415,7 +1419,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/
Segher: I'd appreciate if you could take a look and ack it if this looks OK from a PowerPC perspective.
Looks okay to me. Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
On Wed, May 26, 2010 at 12:34:49AM +0200, Carl-Daniel Hailfinger wrote:
Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian)
Build-tested on x86 and x86_64. Runtime-tested on a random FWH-board/-chip (PREW) on Linux x86_64, still works fine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Index: flashrom-arch_abstraction/hwaccess.c =================================================================== --- flashrom-arch_abstraction/hwaccess.c (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.c (Arbeitskopie) [...] +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +static inline void sync_primitive(void) +{ + asm("eieio" : : : "memory");
This asm could use a nice long comment about what it does exactly and why it's needed etc.
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +#error Unable to determine endianness. Please add support for your arch or libc. +#endif + +#define ___constant_swab8(x) ((uint8_t)( \ ^ space here, please
+ (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ ^
+ (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ ^
+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ ^ Ditto for these other 3 places.
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PCI port I/O is not yet implemented on PowerPC. */ + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* PCI port I/O is not yet implemented on MIPS. */ + +#else + +#error Unknown architecture, please check if it supports PCI port IO. ^^ "IO" -> "I/O" for consistency.
Index: flashrom-arch_abstraction/nic3com.c =================================================================== --- flashrom-arch_abstraction/nic3com.c (Revision 1008) +++ flashrom-arch_abstraction/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h"
+#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unsupported architecture for nic3com. You need a way to emulate port IO access.
"IO" -> "I/O" for consistency. Also, wouldn't the nicrealtek code need the same #ifdefs and #error? Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org
Thanks everyone for reviewing this! New patch, addresses Uwe's comments and incorporates Segher's suggestions for explanatory wording for eieieo on PowerPC. Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Misha Manulis for testing early versions of this patch on PowerPC (big endian) with the satasii programmer. Thanks to Segher Boessenkool for design review and for helping out with compiler tricks and pointing out that we need eieio on PowerPC. Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). Thanks to Uwe Hermann for compile and runtime testing on x86_64. DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH! Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> Index: flashrom-arch_abstraction/hwaccess.c =================================================================== --- flashrom-arch_abstraction/hwaccess.c (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.c (Arbeitskopie) @@ -26,6 +26,15 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + +/* sync primitive is not needed because x86 uses uncached accesses + * which have a strongly ordered memory model. + */ +static inline void sync_primitive(void) +{ +} + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,19 +63,68 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +static inline void sync_primitive(void) +{ + /* Prevent reordering and/or merging of reads/writes to hardware. + * Such reordering and/or merging would break device accesses which + * depend on the exact access order. + */ + asm("eieio" : : : "memory"); +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void release_io_perms(void) +{ +} + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses + * in mode 2 which has a strongly ordered memory model. + */ +static inline void sync_primitive(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; + sync_primitive(); } void mmio_writew(uint16_t val, void *addr) { *(volatile uint16_t *) addr = val; + sync_primitive(); } void mmio_writel(uint32_t val, void *addr) { *(volatile uint32_t *) addr = val; + sync_primitive(); } uint8_t mmio_readb(void *addr) @@ -83,3 +141,33 @@ { return *(volatile uint32_t *) addr; } + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-arch_abstraction/flash.h =================================================================== --- flashrom-arch_abstraction/flash.h (Revision 1008) +++ flashrom-arch_abstraction/flash.h (Arbeitskopie) @@ -63,8 +63,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -407,6 +409,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -603,6 +611,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -610,6 +619,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-arch_abstraction/spi25.c =================================================================== --- flashrom-arch_abstraction/spi25.c (Revision 1008) +++ flashrom-arch_abstraction/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -996,11 +998,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-arch_abstraction/hwaccess.h =================================================================== --- flashrom-arch_abstraction/hwaccess.h (Revision 1008) +++ flashrom-arch_abstraction/hwaccess.h (Arbeitskopie) @@ -24,13 +24,139 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#if defined (__i386__) || defined (__x86_64__) + +/* All x86 is little-endian. */ +#define __FLASHROM_LITTLE_ENDIAN__ 1 + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* MIPS can be either endian. */ +#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL) +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB) +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif + +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PowerPC can be either endian. */ +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) +#define __FLASHROM_BIG_ENDIAN__ 1 +/* Error checking in case some weird header has #defines for LE as well. */ +#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__) +#error Conflicting endianness #define +#endif +#else +#error Little-endian PowerPC #defines are unknown +#endif + +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +/* Nonstandard libc-specific macros for determining endianness. */ +#if defined(__GLIBC__) +#include <endian.h> +#if BYTE_ORDER == LITTLE_ENDIAN +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif BYTE_ORDER == BIG_ENDIAN +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif +#endif +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +#error Unable to determine endianness. Please add support for your arch or libc. +#endif + +#define ___constant_swab8(x) ((uint8_t) ( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t) ( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t) ( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t) ( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (__FLASHROM_BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#elif defined (__FLASHROM_LITTLE_ENDIAN__) + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#else + +#error Could not determine endianness. + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + +#define __FLASHROM_HAVE_OUTB__ 1 + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +288,18 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PCI port I/O is not yet implemented on PowerPC. */ + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* PCI port I/O is not yet implemented on MIPS. */ + +#else + +#error Unknown architecture, please check if it supports PCI port IO. + +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-arch_abstraction/it87spi.c =================================================================== --- flashrom-arch_abstraction/it87spi.c (Revision 1008) +++ flashrom-arch_abstraction/it87spi.c (Arbeitskopie) @@ -23,6 +23,8 @@ * Contains the ITE IT87* SPI specific routines */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include <stdlib.h> #include "flash.h" @@ -351,3 +353,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/physmap.c =================================================================== --- flashrom-arch_abstraction/physmap.c (Revision 1008) +++ flashrom-arch_abstraction/physmap.c (Arbeitskopie) @@ -241,6 +241,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -462,4 +464,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-arch_abstraction/nicrealtek.c =================================================================== --- flashrom-arch_abstraction/nicrealtek.c (Revision 1008) +++ flashrom-arch_abstraction/nicrealtek.c (Arbeitskopie) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <stdlib.h> #include <string.h> #include <sys/types.h> @@ -87,3 +89,7 @@ return val ; } + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif Index: flashrom-arch_abstraction/spi.c =================================================================== --- flashrom-arch_abstraction/spi.c (Revision 1008) +++ flashrom-arch_abstraction/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-arch_abstraction/nic3com.c =================================================================== --- flashrom-arch_abstraction/nic3com.c (Revision 1008) +++ flashrom-arch_abstraction/nic3com.c (Arbeitskopie) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <stdlib.h> #include <string.h> #include <sys/types.h> @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif Index: flashrom-arch_abstraction/Makefile =================================================================== --- flashrom-arch_abstraction/Makefile (Revision 1008) +++ flashrom-arch_abstraction/Makefile (Arbeitskopie) @@ -124,7 +124,9 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -260,7 +262,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-arch_abstraction/wbsio_spi.c =================================================================== --- flashrom-arch_abstraction/wbsio_spi.c (Revision 1008) +++ flashrom-arch_abstraction/wbsio_spi.c (Arbeitskopie) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -199,3 +201,5 @@ return spi_chip_write_1(flash, buf); } + +#endif Index: flashrom-arch_abstraction/chipset_enable.c =================================================================== --- flashrom-arch_abstraction/chipset_enable.c (Revision 1008) +++ flashrom-arch_abstraction/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1425,7 +1430,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-arch_abstraction/sb600spi.c =================================================================== --- flashrom-arch_abstraction/sb600spi.c (Revision 1008) +++ flashrom-arch_abstraction/sb600spi.c (Arbeitskopie) @@ -21,6 +21,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -166,3 +168,5 @@ return 0; } + +#endif Index: flashrom-arch_abstraction/flashrom.c =================================================================== --- flashrom-arch_abstraction/flashrom.c (Revision 1008) +++ flashrom-arch_abstraction/flashrom.c (Arbeitskopie) @@ -276,6 +276,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -293,6 +294,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { @@ -1208,17 +1210,22 @@ #endif #endif #ifdef __clang__ - msg_ginfo(" LLVM %i/clang %i", __llvm__, __clang__); + msg_ginfo(" LLVM %i/clang %i, ", __llvm__, __clang__); #elif defined(__GNUC__) msg_ginfo(" GCC"); #ifdef __VERSION__ - msg_ginfo(" %s", __VERSION__); + msg_ginfo(" %s,", __VERSION__); #else - msg_ginfo(" unknown version"); + msg_ginfo(" unknown version,"); #endif #else - msg_ginfo(" unknown compiler"); + msg_ginfo(" unknown compiler,"); #endif +#if defined (__FLASHROM_LITTLE_ENDIAN__) + msg_ginfo(" little endian"); +#else + msg_ginfo(" big endian"); +#endif msg_ginfo("\n"); } Index: flashrom-arch_abstraction/internal.c =================================================================== --- flashrom-arch_abstraction/internal.c (Revision 1008) +++ flashrom-arch_abstraction/internal.c (Arbeitskopie) @@ -99,10 +99,12 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; int force_boardmismatch = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -112,8 +114,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -166,10 +169,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) { @@ -203,8 +209,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-arch_abstraction/ichspi.c =================================================================== --- flashrom-arch_abstraction/ichspi.c (Revision 1008) +++ flashrom-arch_abstraction/ichspi.c (Arbeitskopie) @@ -33,6 +33,8 @@ * */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -832,3 +834,5 @@ } return ret; } + +#endif Index: flashrom-arch_abstraction/print_wiki.c =================================================================== --- flashrom-arch_abstraction/print_wiki.c (Revision 1008) +++ flashrom-arch_abstraction/print_wiki.c (Arbeitskopie) @@ -104,6 +104,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_url boards_url[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." }, { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, @@ -279,8 +280,10 @@ { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, /* EPIA-N link for now */ { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&m..." }, { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." }, { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, @@ -298,18 +301,23 @@ { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, +#endif /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." }, { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo30..." }, +#endif /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", NULL }, { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&..." }, { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, +#endif { NULL, NULL, 0 }, }; @@ -317,6 +325,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_notes boards_notes[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, @@ -324,23 +333,30 @@ { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, { "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." }, { "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" }, +#endif /* Verified working boards that DO need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, +#endif /* Verified working laptops. */ /* None which need comments, yet... */ /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, +#endif { NULL, NULL, 0 }, }; Index: flashrom-arch_abstraction/print.c =================================================================== --- flashrom-arch_abstraction/print.c (Revision 1008) +++ flashrom-arch_abstraction/print.c (Arbeitskopie) @@ -257,6 +257,7 @@ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", }, { "Abit", "Fatal1ty F-I90HD", }, { "Advantech", "PCM-5820", }, @@ -377,13 +378,14 @@ { "VIA", "pc2500e", }, { "VIA", "PC3500G", }, { "VIA", "VB700X", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_bad[] = { /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", }, { "ASRock", "K7VT4A+", }, { "ASUS", "MEW-AM", }, @@ -401,29 +403,31 @@ { "Sun", "Fire x4200", }, { "Sun", "Fire x4540", }, { "Sun", "Fire x4600", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_ok[] = { /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Lenovo", "3000 V100 TF05Cxx", }, { "Acer", "Aspire 1520", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_bad[] = { /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", }, { "ASUS", "Eee PC 701 4G", }, { "Dell", "Latitude CPi A366XT", }, { "HP/Compaq", "nx9010", }, { "IBM/Lenovo", "Thinkpad T40p", }, { "IBM/Lenovo", "240", }, - +#endif {}, }; #endif Index: flashrom-arch_abstraction/board_enable.c =================================================================== --- flashrom-arch_abstraction/board_enable.c (Revision 1008) +++ flashrom-arch_abstraction/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1306,6 +1307,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1349,6 +1352,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1415,7 +1419,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/
On 26.05.2010 02:49, Carl-Daniel Hailfinger wrote:
Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian)
No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them.
DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH!
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
And committed in r1013. Regards, Carl-Daniel -- http://www.hailfinger.org/
Misha, could you please test this patch with the satasii programmer on your CurtisWright Raptor and ack it if it works? A verbose log from a successful write would be appreciated. The patch applies on top of an otherwise unpatched tree with latest flashrom from svn. Convert all PCI-based external programmers to use special little-endian accessors for all MMIO regions of PCI devices. This patch does _not_ touch the internal programmer (which is PCI-based as well). Huge thanks go to Misha Manulis who worked with me to create a first version of this patch for the satasii programmer based on modification of generic code. To test on x86, compile flashrom normally. To test on non-x86, please run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Index: flashrom-pci_endian/flash.h =================================================================== --- flashrom-pci_endian/flash.h (Revision 1013) +++ flashrom-pci_endian/flash.h (Arbeitskopie) @@ -403,6 +403,8 @@ uint32_t internal_chip_readl(const chipaddr addr); void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); #endif + +/* hwaccess.c */ void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); @@ -415,6 +417,12 @@ uint8_t mmio_le_readb(void *addr); uint16_t mmio_le_readw(void *addr); uint32_t mmio_le_readl(void *addr); +#define pci_mmio_writeb mmio_le_writeb +#define pci_mmio_writew mmio_le_writew +#define pci_mmio_writel mmio_le_writel +#define pci_mmio_readb mmio_le_readb +#define pci_mmio_readw mmio_le_readw +#define pci_mmio_readl mmio_le_readl /* programmer.c */ int noop_shutdown(void); Index: flashrom-pci_endian/drkaiser.c =================================================================== --- flashrom-pci_endian/drkaiser.c (Revision 1013) +++ flashrom-pci_endian/drkaiser.c (Arbeitskopie) @@ -70,10 +70,10 @@ void drkaiser_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, drkaiser_bar + addr); + pci_mmio_writeb(val, drkaiser_bar + addr); } uint8_t drkaiser_chip_readb(const chipaddr addr) { - return mmio_readb(drkaiser_bar + addr); + return pci_mmio_readb(drkaiser_bar + addr); } Index: flashrom-pci_endian/gfxnvidia.c =================================================================== --- flashrom-pci_endian/gfxnvidia.c (Revision 1013) +++ flashrom-pci_endian/gfxnvidia.c (Arbeitskopie) @@ -95,10 +95,10 @@ void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, nvidia_bar + addr); + pci_mmio_writeb(val, nvidia_bar + addr); } uint8_t gfxnvidia_chip_readb(const chipaddr addr) { - return mmio_readb(nvidia_bar + addr); + return pci_mmio_readb(nvidia_bar + addr); } Index: flashrom-pci_endian/satasii.c =================================================================== --- flashrom-pci_endian/satasii.c (Revision 1013) +++ flashrom-pci_endian/satasii.c (Arbeitskopie) @@ -62,7 +62,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -82,32 +82,32 @@ { uint32_t ctrl_reg, data_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; + pci_mmio_writel(data_reg, (sii_bar + 4)); + pci_mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ; } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - mmio_writel(ctrl_reg, sii_bar); + pci_mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ; - return (mmio_readl(sii_bar + 4)) & 0xff; + return (pci_mmio_readl(sii_bar + 4)) & 0xff; } -- http://www.hailfinger.org/
participants (5)
-
Carl-Daniel Hailfinger -
Michael Manulis -
Segher Boessenkool -
Uwe Hermann -
Vladimir 'φ-coder/phcoder' Serbinenko