>From dfa7208a3ebdcae807c96a5279571d449760bec4 Mon Sep 17 00:00:00 2001
From: Tadas Slotkus <devtadas@gmail.com>
Date: Wed, 17 Aug 2011 15:42:37 +0300
Subject: [carFl mem 18/21] Move flashbase and ichspi_bbar to globals

Move flashbase and ichspi_bbar to globals structure.

Signed-off-by: Tadas Slotkus <devtadas@gmail.com>
---
 chipset_enable.c   |    4 ++--
 flash.h            |    5 +++++
 flashrom.c         |    8 +++-----
 ichspi.c           |   32 +++++++++++++++-----------------
 processor_enable.c |    2 +-
 programmer.h       |    2 --
 spi.c              |    2 +-
 7 files changed, 27 insertions(+), 28 deletions(-)

diff --git a/chipset_enable.c b/chipset_enable.c
index c534dcc..9f15ade 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1035,10 +1035,10 @@ static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
 	if (bootcs_found) {
 		if (parx & (1 << 25)) {
 			parx &= (1 << 14) - 1; /* Mask [13:0] */
-			flashbase = parx << 16;
+			g->flashbase = parx << 16;
 		} else {
 			parx &= (1 << 18) - 1; /* Mask [17:0] */
-			flashbase = parx << 12;
+			g->flashbase = parx << 12;
 		}
 	} else {
 		msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
diff --git a/flash.h b/flash.h
index 253e5d9..304db13 100644
--- a/flash.h
+++ b/flash.h
@@ -310,6 +310,11 @@ struct globals {
 #define SUPERIO_MAX_COUNT 3
 	struct superio superios[SUPERIO_MAX_COUNT];
 	int superio_count;
+
+	/* If nonzero, used as the start address of bottom-aligned flash. */
+	unsigned long flashbase;
+
+	uint32_t ichspi_bbar;
 };
 globals *get_globals(void);
 
diff --git a/flashrom.c b/flashrom.c
index ba19a47..252a6c3 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -106,6 +106,7 @@ static void init_globals(void)
 	g.partvendor_from_cbtable = 0;
 	g.has_dmi_support = 0;
 	g.superio_count = 0;
+	g.ichspi_bbar = 0;
 	sync_all_globals();
 }
 
@@ -117,9 +118,6 @@ static char *programmer_param = NULL;
  */
 struct decode_sizes max_rom_decode;
 
-/* If nonzero, used as the start address of bottom-aligned flash. */
-unsigned long flashbase;
-
 /* Is writing allowed with this programmer? */
 int programmer_may_write;
 
@@ -506,7 +504,7 @@ int programmer_init(char *param)
 	};
 	g.buses_supported = BUS_NONE;
 	/* Default to top aligned flash at 4 GB. */
-	flashbase = 0;
+	g.flashbase = 0;
 	/* Registering shutdown functions is now allowed. */
 	may_register_shutdown = 1;
 	/* Default to allowing writes. Broken programmers set this to 0. */
@@ -1157,7 +1155,7 @@ int probe_flash(int startchip, struct flashchip *fill_flash, int force)
 		/* Start filling in the dynamic data. */
 		*fill_flash = *flash;
 
-		base = flashbase ? flashbase : (0xffffffff - size + 1);
+		base = g.flashbase ? g.flashbase : (0xffffffff - size + 1);
 		fill_flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size);
 
 		if (force)
diff --git a/ichspi.c b/ichspi.c
index 531b96b..def557b 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -170,8 +170,6 @@ void sync_globals12(void)
 /* ICH SPI configuration lock-down. May be set during chipset enabling. */
 static int ichspi_lock = 0;
 
-uint32_t ichspi_bbar = 0;
-
 static void *ich_spibar = NULL;
 
 typedef struct _OPCODE {
@@ -571,20 +569,20 @@ static void ich_set_bbar(uint32_t min_addr)
 		return;
 	}
 	
-	ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
-	if (ichspi_bbar) {
+	g->ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
+	if (g->ichspi_bbar) {
 		msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
-			 ichspi_bbar);
+			 g->ichspi_bbar);
 	}
 	min_addr &= BBAR_MASK;
-	ichspi_bbar |= min_addr;
-	rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
-	ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
+	g->ichspi_bbar |= min_addr;
+	rmmio_writel(g->ichspi_bbar, ich_spibar + bbar_off);
+	g->ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
 
 	/* We don't have any option except complaining. And if the write
 	 * failed, the restore will fail as well, so no problem there.
 	 */
-	if (ichspi_bbar != min_addr)
+	if (g->ichspi_bbar != min_addr)
 		msg_perr("Setting BBAR failed!\n");
 }
 
@@ -1018,10 +1016,10 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
 		case SPI_CONTROLLER_ICH7:
 		case SPI_CONTROLLER_VIA:
 		case SPI_CONTROLLER_ICH9:
-			if (addr < ichspi_bbar) {
+			if (addr < g->ichspi_bbar) {
 				msg_perr("%s: Address 0x%06x below allowed "
 					 "range 0x%06x-0xffffff\n", __func__,
-					 addr, ichspi_bbar);
+					 addr, g->ichspi_bbar);
 				return SPI_INVALID_ADDRESS;
 			}
 			break;
@@ -1238,9 +1236,9 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 			msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
 				     mmio_readl(ich_spibar + offs + 4), i);
 		}
-		ichspi_bbar = mmio_readl(ich_spibar + 0x50);
+		g->ichspi_bbar = mmio_readl(ich_spibar + 0x50);
 		msg_pdbg("0x50: 0x%08x (BBAR)\n",
-			     ichspi_bbar);
+			     g->ichspi_bbar);
 		msg_pdbg("0x54: 0x%04x     (PREOP)\n",
 			     mmio_readw(ich_spibar + 0x54));
 		msg_pdbg("0x56: 0x%04x     (OPTYPE)\n",
@@ -1316,9 +1314,9 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 			     mmio_readl(ich_spibar + ICH9_REG_OPMENU));
 		msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
 			     mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4));
-		ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
+		g->ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
 		msg_pdbg("0xA0: 0x%08x (BBAR)\n",
-			     ichspi_bbar);
+			     g->ichspi_bbar);
 		tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
 		msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
 
@@ -1381,8 +1379,8 @@ int via_init_spi(struct pci_dev *dev)
 		msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
 			 mmio_readl(ich_spibar + offs + 4), i);
 	}
-	ichspi_bbar = mmio_readl(ich_spibar + 0x50);
-	msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
+	g->ichspi_bbar = mmio_readl(ich_spibar + 0x50);
+	msg_pdbg("0x50: 0x%08x (BBAR)\n", g->ichspi_bbar);
 	msg_pdbg("0x54: 0x%04x     (PREOP)\n", mmio_readw(ich_spibar + 0x54));
 	msg_pdbg("0x56: 0x%04x     (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
 	msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
diff --git a/processor_enable.c b/processor_enable.c
index 7dab6ee..d627ba7 100644
--- a/processor_enable.c
+++ b/processor_enable.c
@@ -92,7 +92,7 @@ int processor_flash_enable(void)
 	/* FIXME: detect loongson on FreeBSD and OpenBSD as well.  */
 #if defined (__MIPSEL__) && defined (__linux)
 	if (is_loongson()) {
-		flashbase = 0x1fc00000;
+		g->flashbase = 0x1fc00000;
 		return 0;
 	}
 #endif
diff --git a/programmer.h b/programmer.h
index e5d3b6f..a31f3fd 100644
--- a/programmer.h
+++ b/programmer.h
@@ -431,7 +431,6 @@ struct decode_sizes {
 };
 extern struct decode_sizes max_rom_decode;
 extern int programmer_may_write;
-extern unsigned long flashbase;
 void check_chip_supported(const struct flashchip *flash);
 int check_max_decode(enum chipbustype buses, uint32_t size);
 char *extract_programmer_param(const char *param_name);
@@ -497,7 +496,6 @@ void register_spi_programmer(const struct spi_programmer *programmer);
 
 /* ichspi.c */
 #if CONFIG_INTERNAL == 1
-extern uint32_t ichspi_bbar;
 int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 		    int ich_generation);
 int via_init_spi(struct pci_dev *dev);
diff --git a/spi.c b/spi.c
index cc5d61e..b5368c8 100644
--- a/spi.c
+++ b/spi.c
@@ -190,7 +190,7 @@ uint32_t spi_get_valid_read_addr(void)
 #if defined(__i386__) || defined(__x86_64__)
 	case SPI_CONTROLLER_ICH7:
 		/* Return BBAR for ICH chipsets. */
-		return ichspi_bbar;
+		return g->ichspi_bbar;
 #endif
 #endif
 	default:
-- 
1.7.6

