On Wed, Sep 15, 2010 at 16:34, Joshua Roys <roysjosh(a)gmail.com> wrote:
Awesome! I'm glad you got it working.
On 09/15/2010 06:19 AM, Carl-Daniel Hailfinger wrote:
Funny. The 0xc6f access looks very similar to
parts of the SB400 chipset
enable. (Side note: we should ask AMD if the SB400 chipset enable is
Yes, I noticed the same thing- hence the placement in chipset_enable.c.
Joshua, I would like this in 0.9.3. Would it be
OK for you to split the
patch in a chipset enable and a flash chip addition? If possible,
coordinate with Mattias to avoid conflicts in flashchips.[ch]
OK, attached are two separate patches and a diff... if the chip #define
fixup gets applied first, then use the post-prefix-change.diff.txt and
squash it in with the flash chip patch. Otherwise that patch will have
to be updated in order to account for these chips. (I'll try to figure
out on IRC what order these will be in, and if needs be I can spin
another patch set.)
Signed-off-by: Joshua Roys <roysjosh(a)gmail.com>
Flash chip part
Acked-by: Mattias Mattsson <vitplister(a)gmail.com>
Fixed a small typo (TEST_PR -> TEST_OK_PR), added two more Bright chip
IDs and committed as r1176.