Hello Team,
Hope you are doing well. I would like bring this activity in your notice https://review.coreboot.org/q/topic:PCH_HW_SEQ_Cleanup and seek help to review the code.
The reason for this refactoring of HW sequencing SPI driver code are: 1. We (Chrome OS team) recently ran into a firmware update issue on dogfooders (test device utilise by real users and share feedback) systems, where the attempt to perform SPI flash update operation from host-cpu (using underlying flashrom utility) is silently failing. Furthermore, we debug the issue with help of Intel and figure out the problem is related to multiple master is accessing the SPI flash and operation triggered by host-cpu side using flashrom (write and erase operation) is getting timed out (due to given lesser timeout boundary) due to underlying SPI bus is occupied by other master. This is the special case, starting from Tiger Lake Chrome Platform, where we have enable the PVAP (Protected Audio Video Path) which request CSE to perform some erase and write operation as needed. Now an attempt to perform firmware update from host-cpu side might coincide with the CSE performing SPI operations. The recommendation that coming out from Intel is to account the multiple master SPI operation while we are issuing the timeout from flashrom side. We are also expecting a doc update from Intel to share the exact timeout calculation (although I have attempted to document that early here https://review.coreboot.org/c/flashrom/+/62867/1/ichspi.c#35). 2. Maintain the code symmetry between coreboot and flashrom SPI hardware sequencing operations.
From the testing side, I have tested this code on Alderlake `Brya`, Tigerlake `volteer` and Kabylake `eve` devices, and looking for help from community to check on other systems as well (if possible). Furthermore, I have attempted to increase the timeout which won't impact the flashrom performance on the older and/or existing systems.
Looking forward for your help on this request.
Thanks, Subrata