On Tue, 27 Mar 2012 01:40:30 +0530you are right with your diagnosis afaics. when i implemented hwseq i
narayanan best <narayananbest@gmail.com> wrote:
> > > I believe the cause is due to hardware sequencing write does not disable
> > > SRPL (sector protection register lock). I used -p
> > > internal:ich_spi_force=yes option which didn't help.
> > >
> > > This was confirmed when i gave ich_spi_mode=swseq (read or write) as
> > > parameter, it disables the SRPL and next write of 16MB with hardware
> > > sequencing succeeded.
was not thinking about setups like yours. hwseq abstracts away so many
aspects of the write process that it did not make a lot of sense to
think about chip-specific write protections. but in the case hwseq is
only used to be able to access two flash chips, it is (apparently) a
viable use case for some.
are you involved in the design of that specific machine and are you
able to change the firmware? in that case i wonder why you made the
design choice to use chip-specific write protections instead of the
ones provided by the chipset.
if you bought it completely i would like to know which board that is.
in any case, changing flashrom to unlock the first flash chip with sw
sequencing and then doing the rest of the process with hwseq would be a
major effort. a possible workaround is to use swseq to access the first
chip and hwseq for the other half. this could be done with layout
files, see manpage for details please (layout files do only work for
writing at the moment. patches exist for the other operation modes too,
but they are not committed yet. this does not really affect you,
because you only need a workaround for writing anyway).
i also spotted a bug in ich_descriptors.c that showed up in your log.
line 822 should be
" if (nr > 5) {"
instead of
" if (nr >= 5) {"
would be nice if you could recompile with that change and post another
log.
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner