Hello,

About changeset 1173 (http://flashrom.org/trac/flashrom/changeset/1173).

Documentation about registers of AMD southbridges (SP5100) can be found at http://support.amd.com/us/Embedded_TechDocs/44413.pdf

I'm thinking that good way to avoid IMC interaction is to take LPC ownership. this can be done by using HostOwnLPC semaphore (p 271 and p 283):

write 1 in this register
then read this register
if read is 1 => we have LPC ownership,
else we have to retry (IMC has LPC ownership)


I did a try in SB700 registering function, and taking ownership in this way seems to solve the issue: I can read the flash (not tested with write)
But I don't have a great knowledge on flashrom architecture, and I don't know where I can put the code for releasing this semaphore
(simple: write 0 in the register)

Best regards

--
Fred