# flashrom -r backup.bin -VV<br>flashrom v0.9.5-r1503 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.9, GCC 4.6.2 20120120 (prerelease), little endian<br>flashrom is free software, get the source code at <a href="http://www.flashrom.org">http://www.flashrom.org</a><br>
<br>Calibrating delay loop... OS timer resolution is 1 usecs, 1797M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10011 us, 4 myus = 4 us, OK.<br>Initializing internal programmer<br>
No coreboot table found.<br>sh: dmidecode: command not found<br>dmidecode execution unsuccessful - continuing without DMI info<br>Found chipset &quot;Intel ICH8DH&quot; with PCI ID 8086:2812. Enabling flash write... <br>0xfff80000/0xffb80000 FWH IDSEL: 0x0<br>
0xfff00000/0xffb00000 FWH IDSEL: 0x0<br>0xffe80000/0xffa80000 FWH IDSEL: 0x1<br>0xffe00000/0xffa00000 FWH IDSEL: 0x1<br>0xffd80000/0xff980000 FWH IDSEL: 0x2<br>0xffd00000/0xff900000 FWH IDSEL: 0x2<br>0xffc80000/0xff880000 FWH IDSEL: 0x3<br>
0xffc00000/0xff800000 FWH IDSEL: 0x3<br>0xff700000/0xff300000 FWH IDSEL: 0x4<br>0xff600000/0xff200000 FWH IDSEL: 0x5<br>0xff500000/0xff100000 FWH IDSEL: 0x6<br>0xff400000/0xff000000 FWH IDSEL: 0x7<br>0xfff80000/0xffb80000 FWH decode enabled<br>
0xfff00000/0xffb00000 FWH decode enabled<br>0xffe80000/0xffa80000 FWH decode disabled<br>0xffe00000/0xffa00000 FWH decode disabled<br>0xffd80000/0xff980000 FWH decode disabled<br>0xffd00000/0xff900000 FWH decode disabled<br>
0xffc80000/0xff880000 FWH decode disabled<br>0xffc00000/0xff800000 FWH decode disabled<br>0xff700000/0xff300000 FWH decode disabled<br>0xff600000/0xff200000 FWH decode disabled<br>0xff500000/0xff100000 FWH decode disabled<br>
0xff400000/0xff000000 FWH decode disabled<br>Maximum FWH chip size: 0x100000 bytes<br>BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2<br>WARNING: Setting 0xdc from 0x2 to 0x3 on ICH8DH failed. New value is 0x2.<br>
Root Complex Register Block address = 0xfed1c000<br>GCS = 0x880464: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI)<br>Top Swap : not enabled<br>SPIBAR = 0xfed1c000 + 0x3020<br>0x04: 0xe008 (HSFS)<br>HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1<br>
WARNING: SPI Configuration Lockdown activated.<br>Reading OPCODES... done<br>        OP        Type      Pre-OP<br>op[0]: 0x9f, read  w/o addr, none<br>op[1]: 0xab, read  w/  addr, none<br>op[2]: 0x00, read  w/o addr, none<br>
op[3]: 0x00, read  w/o addr, none<br>op[4]: 0x00, read  w/o addr, none<br>op[5]: 0x00, read  w/o addr, none<br>op[6]: 0x00, read  w/o addr, none<br>op[7]: 0x00, read  w/o addr, none<br>Pre-OP 0: 0x00, Pre-OP 1: 0x00<br>0x06: 0x3f00 (HSFC)<br>
HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0<br>0x08: 0x00003000 (FADDR)<br>0x50: 0x00000a0b (FRAP)<br>BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b<br>0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br>
0x58: 0x00ff0035 FREG1: BIOS region (0x00035000-0x000fffff) is read-write.<br>0x5C: 0x00340003 FREG2: WARNING: Management Engine region (0x00003000-0x00034fff) is locked.<br>0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write.<br>
0x64: 0x00000000 FREG4: WARNING: Platform Data region (0x00000000-0x00000fff) is locked.<br>0x74: 0x00000000 (PR0 is unused)<br>0x78: 0x00000000 (PR1 is unused)<br>0x7C: 0x00000000 (PR2 is unused)<br>0x80: 0x00000000 (PR3 is unused)<br>
0x84: 0x00000000 (PR4 is unused)<br>Please send a verbose log to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if this board is not listed on<br><a href="http://flashrom.org/Supported_hardware#Supported_mainboards">http://flashrom.org/Supported_hardware#Supported_mainboards</a> yet.<br>
Writes have been disabled. You can enforce write support with the<br>ich_spi_force programmer option, but it will most likely harm your hardware!<br>If you force flashrom you will get no support if something breaks.<br>0x90: 0x04 (SSFS)<br>
SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0<br>0x91: 0x004200 (SSFC)<br>SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0<br>0x94: 0x0000     (PREOP)<br>0x96: 0x0008     (OPTYPE)<br>0x98: 0x0000ab9f (OPMENU)<br>0x9C: 0x00000000 (OPMENU+4)<br>
0xC1: 0xffffffff (VSCC)<br>VSCC: BES=0x3, WG=1, WSR=1, WEWS=1, EO=0xff, VCL=1<br><br>Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.<br>=== Content Section ===<br>FLVALSIG 0x0ff0a55a<br>FLMAP0   0x03040001<br>
FLMAP1   0x01100206<br>FLMAP2   0x00000120<br><br>--- Details ---<br>NR          (Number of Regions):                     4<br>FRBA        (Flash Region Base Address):         0x040<br>NC          (Number of Components):                  1<br>
FCBA        (Flash Component Base Address):      0x010<br>ISL         (ICH/PCH Strap Length):                  1<br>FISBA/FPSBA (Flash ICH/PCH Strap Base Address):  0x100<br>NM          (Number of Masters):                     3<br>
FMBA        (Flash Master Base Address):         0x060<br>MSL/PSL     (MCH/PROC Strap Length):                 1<br>FMSBA       (Flash MCH/PROC Strap Base Address): 0x200<br><br>=== Component Section ===<br>FLCOMP   0x00300001<br>
FLILL    0x00000000<br><br>--- Details ---<br>Component 1 density:             1 MB<br>Component 2 is not used.<br>Read Clock Frequency:           20 MHz<br>Read ID and Status Clock Freq.: 20 MHz<br>Write and Erase Clock Freq.:    20 MHz<br>
Fast Read is supported.<br>Fast Read Clock Frequency:      33 MHz<br>No forbidden opcodes.<br><br>=== Region Section ===<br>FLREG0   0x00000000<br>FLREG1   0x00ff0035<br>FLREG2   0x00340003<br>FLREG3   0x00020001<br>FLREG4   0x00000000<br>
<br>--- Details ---<br>Region 0 (Descr.) 0x00000000 - 0x00000fff<br>Region 1 (BIOS  ) 0x00035000 - 0x000fffff<br>Region 2 (ME    ) 0x00003000 - 0x00034fff<br>Region 3 (GbE   ) 0x00001000 - 0x00002fff<br>Region 4 (Platf.) 0x00000000 - 0x00000fff<br>
<br>=== Master Section ===<br>FLMSTR1  0x0a0b0000<br>FLMSTR2  0x0c0d0000<br>FLMSTR3  0x08090218<br><br>--- Details ---<br>      Descr. BIOS ME GbE Platf.<br>BIOS    r     rw      rw     <br>ME      r         rw  rw     <br>
GbE     r             rw     <br><br>Enabling hardware sequencing because some important opcode is locked.<br>SPI Read Configuration: prefetching disabled, caching enabled, PROBLEMS, continuing anyway<br>The following protocols are supported: FWH, Programmer-specific.<br>
Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 1024 kB.<br>There is only one partition containing the whole address space (0x000000 - 0x0fffff).<br>There are 256 erase blocks with 4096 B each.<br>
Found Programmer flash chip &quot;Opaque flash chip&quot; (1024 kB, Programmer-specific) at physical address 0x0.<br>Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x89, id2 0x89, id1 is normal flash content, id2 is normal flash content<br>
Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x89, id2 0x89, id1 is normal flash content, id2 is normal flash content<br>Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>
Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x89, id2 0x89, id1 is normal flash content, id2 is normal flash content<br>
Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x48, id2 0x2a, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>
Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x89, id2 0x89, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x89, id2 0x89, id1 is normal flash content, id2 is normal flash content<br>
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xd3, id2 0x56, id1 is normal flash content, id2 is normal flash content<br>
Found Programmer flash chip &quot;Opaque flash chip&quot; (1024 kB, Programmer-specific).<br>Reading flash... Reading 1048576 bytes starting at 0x000000.<br>Transaction error between offset 0x00003000 and 0x0000303f (= 0x00003000 + 63)!<br>
HSFS: FDONE=1, FCERR=1, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1<br>HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0<br>Read operation failed!<br>FAILED.<br>Restoring PCI config space for 00:1f:0 reg 0xdc<br><br>