>From 2e73ef5ddc6e7f19da4239e30b37c25a4a2ec514 Mon Sep 17 00:00:00 2001
From: Tadas Slotkus <devtadas@gmail.com>
Date: Sun, 21 Aug 2011 00:05:38 +0300
Subject: [carFl mem 47/65] Globalisation pass 3: board_enables...

Also does nothing just passes globals forth
acros funcion calls.

This commit might broke compilation as I have squashed, fixed
"Globalisation pass 3" a lot of times going back and forth and changes
might appear not in right order. Last commit of "Globalisation pass 3"
should fix compilation since there all stuff are "in".

Signed-off-by: Tadas Slotkus <devtadas@gmail.com>
---
 bitbang_spi.c      |    4 +-
 board_enable.c     |  268 ++++++++++++++++++++++++++--------------------------
 chipset_enable.c   |   24 +++---
 dummyflasher.c     |    2 +-
 ichspi.c           |    8 +-
 internal.c         |   16 ++--
 it85spi.c          |    2 +-
 it87spi.c          |    4 +-
 mcp6x_spi.c        |    6 +-
 processor_enable.c |    4 +-
 programmer.h       |   30 +++---
 sb600spi.c         |    6 +-
 spi.c              |    2 +-
 wbsio_spi.c        |    4 +-
 14 files changed, 190 insertions(+), 190 deletions(-)

diff --git a/bitbang_spi.c b/bitbang_spi.c
index 751060a..bb2c2d1 100644
--- a/bitbang_spi.c
+++ b/bitbang_spi.c
@@ -77,7 +77,7 @@ static const struct spi_programmer spi_programmer_bitbang = {
 	.write_256	= default_spi_write_256,
 };
 
-int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod)
+int bitbang_spi_init(globals *g, const struct bitbang_spi_master *master, int halfperiod)
 {
 	/* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type,
 	 * we catch it here. Same goes for missing initialization of bitbanging
@@ -98,7 +98,7 @@ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod)
 	bitbang_spi_master = master;
 	bitbang_spi_half_period = halfperiod;
 
-	register_spi_programmer(&spi_programmer_bitbang);
+	register_spi_programmer(g, &spi_programmer_bitbang);
 
 	/* FIXME: Run bitbang_spi_request_bus here or in programmer init? */
 	bitbang_spi_set_cs(1);
diff --git a/board_enable.c b/board_enable.c
index e798bf4..6270b80 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -69,7 +69,7 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
 
 /* Not used yet. */
 #if 0
-static int enable_flash_decode_superio(void)
+static int enable_flash_decode_superio(globals *g)
 {
 	int ret;
 	uint8_t tmp;
@@ -131,7 +131,7 @@ static int fdc37b787_gpio50_raise(uint16_t port)
  * Suited for:
  *  - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
  */
-static int fdc37b787_gpio50_raise_3f0(void)
+static int fdc37b787_gpio50_raise_3f0(globals *g)
 {
 	return fdc37b787_gpio50_raise(0x3f0);
 }
@@ -317,7 +317,7 @@ static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
  *  - Agami Aruma
  *  - IWILL DK8-HTX
  */
-static int w83627hf_gpio24_raise_2e(void)
+static int w83627hf_gpio24_raise_2e(globals *g)
 {
 	return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
 }
@@ -328,7 +328,7 @@ static int w83627hf_gpio24_raise_2e(void)
  * Suited for:
  *  - MSI MS-6577
  */
-static int w83627hf_gpio25_raise_2e(void)
+static int w83627hf_gpio25_raise_2e(globals *g)
 {
 	return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
 }
@@ -339,7 +339,7 @@ static int w83627hf_gpio25_raise_2e(void)
  * Suited for:
  *  - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
  */
-static int w83627ehf_gpio22_raise_2e(void)
+static int w83627ehf_gpio22_raise_2e(globals *g)
 {
 	return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
 }
@@ -350,7 +350,7 @@ static int w83627ehf_gpio22_raise_2e(void)
  * Suited for:
  *  - MSI K8T Neo2-F
  */
-static int w83627thf_gpio44_raise_2e(void)
+static int w83627thf_gpio44_raise_2e(globals *g)
 {
 	return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
 }
@@ -361,7 +361,7 @@ static int w83627thf_gpio44_raise_2e(void)
  * Suited for:
  *  - MSI K8N Neo3
  */
-static int w83627thf_gpio44_raise_4e(void)
+static int w83627thf_gpio44_raise_4e(globals *g)
 {
 	return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
 }
@@ -393,7 +393,7 @@ static void w836xx_memw_enable(uint16_t port)
  *  - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
  *  - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
  */
-static int w836xx_memw_enable_2e(void)
+static int w836xx_memw_enable_2e(globals *g)
 {
 	w836xx_memw_enable(0x2E);
 
@@ -404,7 +404,7 @@ static int w836xx_memw_enable_2e(void)
  * Suited for:
  *  - Termtek TK-3370 (rev. 2.5b)
  */
-static int w836xx_memw_enable_4e(void)
+static int w836xx_memw_enable_4e(globals *g)
 {
 	w836xx_memw_enable(0x4E);
 
@@ -415,7 +415,7 @@ static int w836xx_memw_enable_4e(void)
  * Suited for all boards with ITE IT8705F.
  * The SIS950 Super I/O probably requires a similar flash write enable.
  */
-int it8705f_write_enable(uint8_t port)
+int it8705f_write_enable(globals *g, uint8_t port)
 {
 	uint8_t tmp;
 	int ret = 0;
@@ -538,7 +538,7 @@ static int it8707f_write_enable(uint8_t port)
  * Suited for:
  *  - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
  */
-static int it8707f_write_enable_2e(void)
+static int it8707f_write_enable_2e(globals *g)
 {
 	return it8707f_write_enable(0x2e);
 }
@@ -590,13 +590,13 @@ static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
 /*
  * VIA VT823x: Set one of the GPIO pins.
  */
-static int via_vt823x_gpio_set(uint8_t gpio, int raise)
+static int via_vt823x_gpio_set(globals *g, uint8_t gpio, int raise)
 {
 	struct pci_dev *dev;
 	uint16_t base;
 	uint8_t val, bit, offset;
 
-	dev = pci_dev_find_vendorclass(0x1106, 0x0601);
+	dev = pci_dev_find_vendorclass(g, 0x1106, 0x0601);
 	switch (dev->device_id) {
 	case 0x3177:	/* VT8235 */
 	case 0x3227:	/* VT8237R */
@@ -647,19 +647,19 @@ static int via_vt823x_gpio_set(uint8_t gpio, int raise)
  * Suited for:
  *  - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
  */
-static int via_vt823x_gpio5_raise(void)
+static int via_vt823x_gpio5_raise(globals *g)
 {
 	/* On M2V-MX: GPO5 is connected to WP# and TBL#. */
-	return via_vt823x_gpio_set(5, 1);
+	return via_vt823x_gpio_set(g, 5, 1);
 }
 
 /*
  * Suited for:
  *  - VIA EPIA EK & N & NL
  */
-static int via_vt823x_gpio9_raise(void)
+static int via_vt823x_gpio9_raise(globals *g)
 {
-	return via_vt823x_gpio_set(9, 1);
+	return via_vt823x_gpio_set(g, 9, 1);
 }
 
 /*
@@ -669,9 +669,9 @@ static int via_vt823x_gpio9_raise(void)
  * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
  * lowered there.
  */
-static int via_vt823x_gpio15_raise(void)
+static int via_vt823x_gpio15_raise(globals *g)
 {
-	return via_vt823x_gpio_set(15, 1);
+	return via_vt823x_gpio_set(g, 15, 1);
 }
 
 /*
@@ -681,11 +681,11 @@ static int via_vt823x_gpio15_raise(void)
  *  - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
  *  - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
  */
-static int board_msi_kt4v(void)
+static int board_msi_kt4v(globals *g)
 {
 	int ret;
 
-	ret = via_vt823x_gpio_set(12, 1);
+	ret = via_vt823x_gpio_set(g, 12, 1);
 	w836xx_memw_enable(0x2E);
 
 	return ret;
@@ -699,7 +699,7 @@ static int board_msi_kt4v(void)
  * We're basically talking to some unknown device on SMBus, my guess
  * is that it is the Winbond W83781D that lives near the DIP BIOS.
  */
-static int board_asus_p5a(void)
+static int board_asus_p5a(globals *g)
 {
 	uint8_t tmp;
 	int i;
@@ -773,7 +773,7 @@ static int board_asus_p5a(void)
  *
  * It's not a Super I/O but it uses the same index/data port method.
  */
-static int board_hp_dl145_g3_enable(void)
+static int board_hp_dl145_g3_enable(globals *g)
 {
 	/* GPIO 0 reg from PM regs */
 	/* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
@@ -787,7 +787,7 @@ static int board_hp_dl145_g3_enable(void)
  *
  * It's not a Super I/O but it uses the same index/data port method.
  */
-static int board_hp_dl165_g6_enable(void)
+static int board_hp_dl165_g6_enable(globals *g)
 {
 	/* Variant of DL145, with slightly different pin placement. */
 	sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
@@ -796,7 +796,7 @@ static int board_hp_dl165_g6_enable(void)
 	return 0;
 }
 
-static int board_ibm_x3455(void)
+static int board_ibm_x3455(globals *g)
 {
 	/* Raise GPIO13. */
 	sio_mask(0xcd6, 0x45, 0x20, 0x20);
@@ -808,11 +808,11 @@ static int board_ibm_x3455(void)
  * Suited for:
  *  - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
  */
-static int board_shuttle_fn25(void)
+static int board_shuttle_fn25(globals *g)
 {
 	struct pci_dev *dev;
 
-	dev = pci_dev_find(0x10DE, 0x0050);	/* NVIDIA CK804 ISA bridge. */
+	dev = pci_dev_find(g, 0x10DE, 0x0050);	/* NVIDIA CK804 ISA bridge. */
 	if (!dev) {
 		msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
 		return -1;
@@ -828,12 +828,12 @@ static int board_shuttle_fn25(void)
  * Suited for:
  * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
  */
-static int board_ecs_geforce6100sm_m(void)
+static int board_ecs_geforce6100sm_m(globals *g)
 {
 	struct pci_dev *dev;
 	uint32_t tmp;
 
-	dev = pci_dev_find(0x10DE, 0x03EB);     /* NVIDIA MCP61 SMBus. */
+	dev = pci_dev_find(g, 0x10DE, 0x03EB);     /* NVIDIA MCP61 SMBus. */
 	if (!dev) {
 		msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
 		return -1;
@@ -849,7 +849,7 @@ static int board_ecs_geforce6100sm_m(void)
 /*
  * Very similar to AMD 8111 IO Hub.
  */
-static int nvidia_mcp_gpio_set(int gpio, int raise)
+static int nvidia_mcp_gpio_set(globals *g, int gpio, int raise)
 {
 	struct pci_dev *dev;
 	uint16_t base, devclass;
@@ -861,7 +861,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise)
 	}
 
 	/* First, check the ISA bridge */
-	dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
+	dev = pci_dev_find_vendorclass(g, 0x10DE, 0x0601);
 	switch (dev->device_id) {
 	case 0x0030: /* CK804 */
 	case 0x0050: /* MCP04 */
@@ -925,18 +925,18 @@ static int nvidia_mcp_gpio_set(int gpio, int raise)
  *  - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
  *  - ASUS M2NBP-VM CSM: NVIDIA MCP51
  */
-static int nvidia_mcp_gpio0_raise(void)
+static int nvidia_mcp_gpio0_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x00, 1);
+	return nvidia_mcp_gpio_set(g, 0x00, 1);
 }
 
 /*
  * Suited for:
  *  - abit KN8 Ultra: NVIDIA CK804
  */
-static int nvidia_mcp_gpio2_lower(void)
+static int nvidia_mcp_gpio2_lower(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x02, 0);
+	return nvidia_mcp_gpio_set(g, 0x02, 0);
 }
 
 /*
@@ -945,18 +945,18 @@ static int nvidia_mcp_gpio2_lower(void)
  *  - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
  *  - MSI K8NGM2-L: NVIDIA MCP51
  */
-static int nvidia_mcp_gpio2_raise(void)
+static int nvidia_mcp_gpio2_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x02, 1);
+	return nvidia_mcp_gpio_set(g, 0x02, 1);
 }
 
 /*
  * Suited for:
  *  - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
  */
-static int nvidia_mcp_gpio4_raise(void)
+static int nvidia_mcp_gpio4_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x04, 1);
+	return nvidia_mcp_gpio_set(g, 0x04, 1);
 }
 
 /*
@@ -971,72 +971,72 @@ static int nvidia_mcp_gpio4_raise(void)
  *        b) #TBL is hardwired on that board to a pull-down. It can be
  *           overridden by connecting the two solder points next to F2.
  */
-static int nvidia_mcp_gpio5_raise(void)
+static int nvidia_mcp_gpio5_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x05, 1);
+	return nvidia_mcp_gpio_set(g, 0x05, 1);
 }
 
 /*
  * Suited for:
  *  - abit NF7-S: NVIDIA CK804
  */
-static int nvidia_mcp_gpio8_raise(void)
+static int nvidia_mcp_gpio8_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x08, 1);
+	return nvidia_mcp_gpio_set(g, 0x08, 1);
 }
 
 /*
  * Suited for:
  *  - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3  + CK8
  */
-static int nvidia_mcp_gpio0a_raise(void)
+static int nvidia_mcp_gpio0a_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x0a, 1);
+	return nvidia_mcp_gpio_set(g, 0x0a, 1);
 }
 
 /*
  * Suited for:
  *  - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
  */
-static int nvidia_mcp_gpio0c_raise(void)
+static int nvidia_mcp_gpio0c_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x0c, 1);
+	return nvidia_mcp_gpio_set(g, 0x0c, 1);
 }
 
 /*
  * Suited for:
  *  - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
  */
-static int nvidia_mcp_gpio4_lower(void)
+static int nvidia_mcp_gpio4_lower(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x04, 0);
+	return nvidia_mcp_gpio_set(g, 0x04, 0);
 }
 
 /*
  * Suited for:
  *  - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
  */
-static int nvidia_mcp_gpio10_raise(void)
+static int nvidia_mcp_gpio10_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x10, 1);
+	return nvidia_mcp_gpio_set(g, 0x10, 1);
 }
 
 /*
  * Suited for:
  *  - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
  */
-static int nvidia_mcp_gpio21_raise(void)
+static int nvidia_mcp_gpio21_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x21, 0x01);
+	return nvidia_mcp_gpio_set(g, 0x21, 0x01);
 }
 
 /*
  * Suited for:
  *  - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
  */
-static int nvidia_mcp_gpio31_raise(void)
+static int nvidia_mcp_gpio31_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x31, 0x01);
+	return nvidia_mcp_gpio_set(g, 0x31, 0x01);
 }
 
 /*
@@ -1044,16 +1044,16 @@ static int nvidia_mcp_gpio31_raise(void)
  *  - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
  *  - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
  */
-static int nvidia_mcp_gpio3b_raise(void)
+static int nvidia_mcp_gpio3b_raise(globals *g)
 {
-	return nvidia_mcp_gpio_set(0x3b, 1);
+	return nvidia_mcp_gpio_set(g, 0x3b, 1);
 }
 
 /*
  * Suited for:
  *  - Artec Group DBE61 and DBE62
  */
-static int board_artecgroup_dbe6x(void)
+static int board_artecgroup_dbe6x(globals *g)
 {
 #define DBE6x_MSR_DIVIL_BALL_OPTS	0x51400015
 #define DBE6x_PRI_BOOT_LOC_SHIFT	2
@@ -1097,12 +1097,12 @@ static int board_artecgroup_dbe6x(void)
  * Datasheet(s) used:
  *  - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
  */
-static int amd_sbxxx_gpio9_raise(void)
+static int amd_sbxxx_gpio9_raise(globals *g)
 {
 	struct pci_dev *dev;
 	uint32_t reg;
 
-	dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
+	dev = pci_dev_find(g, 0x1002, 0x4372); /* AMD SMBus controller */
 	if (!dev) {
 		msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
 		return -1;
@@ -1123,7 +1123,7 @@ static int amd_sbxxx_gpio9_raise(void)
 /*
  * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
  */
-static int intel_piix4_gpo_set(unsigned int gpo, int raise)
+static int intel_piix4_gpo_set(globals *g, unsigned int gpo, int raise)
 {
 	unsigned int gpo_byte, gpo_bit;
 	struct pci_dev *dev;
@@ -1166,7 +1166,7 @@ static int intel_piix4_gpo_set(unsigned int gpo, int raise)
 		{0}
 	};
 
-	dev = pci_dev_find(0x8086, 0x7110);	/* Intel PIIX4 ISA bridge */
+	dev = pci_dev_find(g, 0x8086, 0x7110);	/* Intel PIIX4 ISA bridge */
 	if (!dev) {
 		msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
 		return -1;
@@ -1186,7 +1186,7 @@ static int intel_piix4_gpo_set(unsigned int gpo, int raise)
 		return -1;
 	}
 
-	dev = pci_dev_find(0x8086, 0x7113);	/* Intel PIIX4 PM */
+	dev = pci_dev_find(g, 0x8086, 0x7113);	/* Intel PIIX4 PM */
 	if (!dev) {
 		msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
 		return -1;
@@ -1211,60 +1211,60 @@ static int intel_piix4_gpo_set(unsigned int gpo, int raise)
  * Suited for:
  *  - ASUS P2B-N
  */
-static int intel_piix4_gpo18_lower(void)
+static int intel_piix4_gpo18_lower(globals *g)
 {
-	return intel_piix4_gpo_set(18, 0);
+	return intel_piix4_gpo_set(g, 18, 0);
 }
 
 /*
  * Suited for:
  *  - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
  */
-static int intel_piix4_gpo14_raise(void)
+static int intel_piix4_gpo14_raise(globals *g)
 {
-	return intel_piix4_gpo_set(14, 1);
+	return intel_piix4_gpo_set(g, 14, 1);
 }
 
 /*
  * Suited for:
  *  - EPoX EP-BX3
  */
-static int intel_piix4_gpo22_raise(void)
+static int intel_piix4_gpo22_raise(globals *g)
 {
-	return intel_piix4_gpo_set(22, 1);
+	return intel_piix4_gpo_set(g, 22, 1);
 }
 
 /*
  * Suited for:
  *  - abit BM6
  */
-static int intel_piix4_gpo26_lower(void)
+static int intel_piix4_gpo26_lower(globals *g)
 {
-	return intel_piix4_gpo_set(26, 0);
+	return intel_piix4_gpo_set(g, 26, 0);
 }
 
 /*
  * Suited for:
  *  - Intel SE440BX-2
  */
-static int intel_piix4_gpo27_lower(void)
+static int intel_piix4_gpo27_lower(globals *g)
 {
-	return intel_piix4_gpo_set(27, 0);
+	return intel_piix4_gpo_set(g, 27, 0);
 }
 
 /*
  * Suited for:
  *  - Dell OptiPlex GX1
  */
-static int intel_piix4_gpo30_lower(void)
+static int intel_piix4_gpo30_lower(globals *g)
 {
-	return intel_piix4_gpo_set(30, 0);
+	return intel_piix4_gpo_set(g, 30, 0);
 }
 
 /*
  * Set a GPIO line on a given Intel ICH LPC controller.
  */
-static int intel_ich_gpio_set(int gpio, int raise)
+static int intel_ich_gpio_set(globals *g, int gpio, int raise)
 {
 	/* Table mapping the different Intel ICH LPC chipsets. */
 	static struct {
@@ -1463,27 +1463,27 @@ static int intel_ich_gpio_set(int gpio, int raise)
  *  - abit IP35 Pro: Intel P35 + ICH9R
  *  - ASUS P5LD2
  */
-static int intel_ich_gpio16_raise(void)
+static int intel_ich_gpio16_raise(globals *g)
 {
-	return intel_ich_gpio_set(16, 1);
+	return intel_ich_gpio_set(g, 16, 1);
 }
 
 /*
  * Suited for:
  *  - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
  */
-static int intel_ich_gpio18_raise(void)
+static int intel_ich_gpio18_raise(globals *g)
 {
-	return intel_ich_gpio_set(18, 1);
+	return intel_ich_gpio_set(g, 18, 1);
 }
 
 /*
  * Suited for:
  *  - MSI MS-7046: LGA775 + 915P + ICH6
  */
-static int intel_ich_gpio19_raise(void)
+static int intel_ich_gpio19_raise(globals *g)
 {
-	return intel_ich_gpio_set(19, 1);
+	return intel_ich_gpio_set(g, 19, 1);
 }
 
 /*
@@ -1499,9 +1499,9 @@ static int intel_ich_gpio19_raise(void)
  *  - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
  *  - Samsung Polaris 32: socket478 + 865P + ICH5
  */
-static int intel_ich_gpio21_raise(void)
+static int intel_ich_gpio21_raise(globals *g)
 {
-	return intel_ich_gpio_set(21, 1);
+	return intel_ich_gpio_set(g, 21, 1);
 }
 
 /*
@@ -1510,37 +1510,37 @@ static int intel_ich_gpio21_raise(void)
  *  - ASUS P4B533-E: socket478 + 845E + ICH4
  *  - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
  */
-static int intel_ich_gpio22_raise(void)
+static int intel_ich_gpio22_raise(globals *g)
 {
-	return intel_ich_gpio_set(22, 1);
+	return intel_ich_gpio_set(g, 22, 1);
 }
 
 /*
  * Suited for:
  *  - ASUS A8Jm (laptop): Intel 945 + ICH7
  */
-static int intel_ich_gpio34_raise(void)
+static int intel_ich_gpio34_raise(globals *g)
 {
-	return intel_ich_gpio_set(34, 1);
+	return intel_ich_gpio_set(g, 34, 1);
 }
 
 /*
  * Suited for:
  *  - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
  */
-static int intel_ich_gpio43_raise(void)
+static int intel_ich_gpio43_raise(globals *g)
 {
-	return intel_ich_gpio_set(43, 1);
+	return intel_ich_gpio_set(g, 43, 1);
 }
 
 /*
  * Suited for:
  *  - HP Vectra VL400: 815 + ICH + PC87360
  */
-static int board_hp_vl400(void)
+static int board_hp_vl400(globals *g)
 {
 	int ret;
-	ret = intel_ich_gpio_set(25, 1);	/* Master write enable ? */
+	ret = intel_ich_gpio_set(g, 25, 1);	/* Master write enable ? */
 	if (!ret)
 		ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1);	/* #WP ? */
 	if (!ret)
@@ -1552,7 +1552,7 @@ static int board_hp_vl400(void)
  * Suited for:
  *  - HP e-Vectra P2706T: 810E + ICH + PC87364
  */
-static int board_hp_p2706t(void)
+static int board_hp_p2706t(globals *g)
 {
 	int ret;
 	ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
@@ -1568,9 +1568,9 @@ static int board_hp_p2706t(void)
  *  - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
  *  - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
  */
-static int intel_ich_gpio23_raise(void)
+static int intel_ich_gpio23_raise(globals *g)
 {
-	return intel_ich_gpio_set(23, 1);
+	return intel_ich_gpio_set(g, 23, 1);
 }
 
 /*
@@ -1578,18 +1578,18 @@ static int intel_ich_gpio23_raise(void)
  *  - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
  *  - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
  */
-static int intel_ich_gpio25_raise(void)
+static int intel_ich_gpio25_raise(globals *g)
 {
-	return intel_ich_gpio_set(25, 1);
+	return intel_ich_gpio_set(g, 25, 1);
 }
 
 /*
  * Suited for:
  *  - IBASE MB899: i945GM + ICH7
  */
-static int intel_ich_gpio26_raise(void)
+static int intel_ich_gpio26_raise(globals *g)
 {
-	return intel_ich_gpio_set(26, 1);
+	return intel_ich_gpio_set(g, 26, 1);
 }
 
 /*
@@ -1599,16 +1599,16 @@ static int intel_ich_gpio26_raise(void)
  *  - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
  *  - MSI MS-6788-40 (aka 848P Neo-V)
  */
-static int intel_ich_gpio32_raise(void)
+static int intel_ich_gpio32_raise(globals *g)
 {
-	return intel_ich_gpio_set(32, 1);
+	return intel_ich_gpio_set(g, 32, 1);
 }
 
 /*
  * Suited for:
  *  - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
  */
-static int board_aopen_i975xa_ydg(void)
+static int board_aopen_i975xa_ydg(globals *g)
 {
 	int ret;
 
@@ -1621,7 +1621,7 @@ static int board_aopen_i975xa_ydg(void)
 	ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
 	if (!ret)
 */
-		ret = intel_ich_gpio_set(33, 1);
+		ret = intel_ich_gpio_set(g, 33, 1);
 
 	return ret;
 }
@@ -1630,14 +1630,14 @@ static int board_aopen_i975xa_ydg(void)
  * Suited for:
  *  - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
  */
-static int board_acorp_6a815epd(void)
+static int board_acorp_6a815epd(globals *g)
 {
 	int ret;
 
 	/* Lower Blocks Lock -- pin 7 of PLCC32 */
-	ret = intel_ich_gpio_set(22, 1);
+	ret = intel_ich_gpio_set(g, 22, 1);
 	if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
-		ret = intel_ich_gpio_set(23, 1);
+		ret = intel_ich_gpio_set(g, 23, 1);
 
 	return ret;
 }
@@ -1646,13 +1646,13 @@ static int board_acorp_6a815epd(void)
  * Suited for:
  *  - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
  */
-static int board_kontron_986lcd_m(void)
+static int board_kontron_986lcd_m(globals *g)
 {
 	int ret;
 
-	ret = intel_ich_gpio_set(34, 1); /* #TBL */
+	ret = intel_ich_gpio_set(g, 34, 1); /* #TBL */
 	if (!ret)
-		ret = intel_ich_gpio_set(35, 1); /* #WP */
+		ret = intel_ich_gpio_set(g, 35, 1); /* #WP */
 
 	return ret;
 }
@@ -1661,13 +1661,13 @@ static int board_kontron_986lcd_m(void)
  * Suited for:
  *  - Soyo SY-7VCA: Pro133A + VT82C686
  */
-static int via_apollo_gpo_set(int gpio, int raise)
+static int via_apollo_gpo_set(globals *g, int gpio, int raise)
 {
 	struct pci_dev *dev;
 	uint32_t base, tmp;
 
 	/* VT82C686 power management */
-	dev = pci_dev_find(0x1106, 0x3057);
+	dev = pci_dev_find(g, 0x1106, 0x3057);
 	if (!dev) {
 		msg_perr("\nERROR: VT82C686 PM device not found.\n");
 		return -1;
@@ -1713,18 +1713,18 @@ static int via_apollo_gpo_set(int gpio, int raise)
  *  - abit VT6X4: Pro133x + VT82C686A
  *  - abit VA6: Pro133x + VT82C686A
  */
-static int via_apollo_gpo4_lower(void)
+static int via_apollo_gpo4_lower(globals *g)
 {
-	return via_apollo_gpo_set(4, 0);
+	return via_apollo_gpo_set(g, 4, 0);
 }
 
 /*
  * Suited for:
  *  - Soyo SY-7VCA: Pro133A + VT82C686
  */
-static int via_apollo_gpo0_lower(void)
+static int via_apollo_gpo0_lower(globals *g)
 {
-	return via_apollo_gpo_set(0, 0);
+	return via_apollo_gpo_set(g, 0, 0);
 }
 
 /*
@@ -1734,12 +1734,12 @@ static int via_apollo_gpo0_lower(void)
  *  - MSI 651M-L: SiS651 / SiS962
  *  - GIGABYTE GA-8SIMLH
  */
-static int sis_gpio0_raise_and_w836xx_memw(void)
+static int sis_gpio0_raise_and_w836xx_memw(globals *g)
 {
 	struct pci_dev *dev;
 	uint16_t base, temp;
 
-	dev = pci_dev_find(0x1039, 0x0962);
+	dev = pci_dev_find(g, 0x1039, 0x0962);
 	if (!dev) {
 		msg_perr("Expected south bridge not found\n");
 		return 1;
@@ -1797,13 +1797,13 @@ out:
  * Disable write protection on the Mitac 6513WU. WP# on the FWH is
  * connected to GP30 on the Super I/O, and TBL# is always high.
  */
-static int board_mitac_6513wu(void)
+static int board_mitac_6513wu(globals *g)
 {
 	struct pci_dev *dev;
 	uint16_t rt_port;
 	uint8_t val;
 
-	dev = pci_dev_find(0x8086, 0x2410);	/* Intel 82801AA ISA bridge */
+	dev = pci_dev_find(g, 0x8086, 0x2410);	/* Intel 82801AA ISA bridge */
 	if (!dev) {
 		msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
 		return -1;
@@ -1831,7 +1831,7 @@ static int board_mitac_6513wu(void)
  *  - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
  *  - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
  */
-static int it8703f_gpio51_raise(void)
+static int it8703f_gpio51_raise(globals *g)
 {
 	uint16_t id, base;
 	uint8_t tmp;
@@ -1925,7 +1925,7 @@ static int it8712f_gpio_set(unsigned int line, int raise)
  * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
  * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
  */
-static int it8712f_gpio3_1_raise(void)
+static int it8712f_gpio3_1_raise(globals *g)
 {
 	return it8712f_gpio_set(32, 1);
 }
@@ -2112,11 +2112,11 @@ static const struct board_pciid_enable *board_match_coreboot_name(
 		if (!board->lb_part || strcasecmp(board->lb_part, part))
 			continue;
 
-		if (!pci_dev_find(board->first_vendor, board->first_device))
+		if (!pci_dev_find(g, board->first_vendor, board->first_device))
 			continue;
 
 		if (board->second_vendor &&
-		    !pci_dev_find(board->second_vendor, board->second_device))
+		    !pci_dev_find(g, board->second_vendor, board->second_device))
 			continue;
 
 		if (vendor)
@@ -2163,20 +2163,20 @@ const static struct board_pciid_enable *board_match_pci_card_ids(globals *g,
 		if (board->phase != phase)
 			continue;
 
-		if (!pci_card_find(board->first_vendor, board->first_device,
+		if (!pci_card_find(g, board->first_vendor, board->first_device,
 				   board->first_card_vendor,
 				   board->first_card_device))
 			continue;
 
 		if (board->second_vendor) {
 			if (board->second_card_vendor) {
-				if (!pci_card_find(board->second_vendor,
+				if (!pci_card_find(g, board->second_vendor,
 						   board->second_device,
 						   board->second_card_vendor,
 						   board->second_card_device))
 					continue;
 			} else {
-				if (!pci_dev_find(board->second_vendor,
+				if (!pci_dev_find(g, board->second_vendor,
 						  board->second_device))
 					continue;
 			}
@@ -2225,7 +2225,7 @@ static int unsafe_board_handler(globals *g, const struct board_pciid_enable *boa
 }
 
 /* FIXME: Should this be identical to board_flash_enable? */
-static int board_handle_phase(enum board_match_phase phase)
+static int board_handle_phase(globals *g, enum board_match_phase phase)
 {
 	const struct board_pciid_enable *board = NULL;
 
@@ -2243,20 +2243,20 @@ static int board_handle_phase(enum board_match_phase phase)
 		return 0;
 	}
 
-	return board->enable();
+	return board->enable(g);
 }
 
-void board_handle_before_superio(void)
+void board_handle_before_superio(globals *g)
 {
-	board_handle_phase(P1);
+	board_handle_phase(g, P1);
 }
 
-void board_handle_before_laptop(void)
+void board_handle_before_laptop(globals *g)
 {
-	board_handle_phase(P2);
+	board_handle_phase(g, P2);
 }
 
-int board_flash_enable(const char *vendor, const char *part)
+int board_flash_enable(globals *g, const char *vendor, const char *part)
 {
 	const struct board_pciid_enable *board = NULL;
 	int ret = 0;
@@ -2280,7 +2280,7 @@ int board_flash_enable(const char *vendor, const char *part)
 				  "board \"%s %s\"... ", board->vendor_name,
 				  board->board_name);
 
-			ret = board->enable();
+			ret = board->enable(g);
 			if (ret)
 				msg_pinfo("FAILED!\n");
 			else
diff --git a/chipset_enable.c b/chipset_enable.c
index f6b1a71..2fc255b 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -85,15 +85,15 @@ static int enable_flash_sis_mapping(globals *g, struct pci_dev *dev, const char
 	return 0;
 }
 
-static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
+static struct pci_dev *find_southbridge(globals *g, uint16_t vendor, const char *name)
 {
 	struct pci_dev *sbdev;
 
-	sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
+	sbdev = pci_dev_find_vendorclass(g, vendor, 0x0601);
 	if (!sbdev)
-		sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
+		sbdev = pci_dev_find_vendorclass(g, vendor, 0x0680);
 	if (!sbdev)
-		sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
+		sbdev = pci_dev_find_vendorclass(g, vendor, 0x0000);
 	if (!sbdev)
 		msg_perr("No southbridge found for %s!\n", name);
 	if (sbdev)
@@ -109,7 +109,7 @@ static int enable_flash_sis501(globals *g, struct pci_dev *dev, const char *name
 	int ret = 0;
 	struct pci_dev *sbdev;
 
-	sbdev = find_southbridge(dev->vendor_id, name);
+	sbdev = find_southbridge(g, dev->vendor_id, name);
 	if (!sbdev)
 		return -1;
 
@@ -134,7 +134,7 @@ static int enable_flash_sis5511(globals *g, struct pci_dev *dev, const char *nam
 	int ret = 0;
 	struct pci_dev *sbdev;
 
-	sbdev = find_southbridge(dev->vendor_id, name);
+	sbdev = find_southbridge(g, dev->vendor_id, name);
 	if (!sbdev)
 		return -1;
 
@@ -154,7 +154,7 @@ static int enable_flash_sis530(globals *g, struct pci_dev *dev, const char *name
 	int ret = 0;
 	struct pci_dev *sbdev;
 
-	sbdev = find_southbridge(dev->vendor_id, name);
+	sbdev = find_southbridge(g, dev->vendor_id, name);
 	if (!sbdev)
 		return -1;
 
@@ -181,7 +181,7 @@ static int enable_flash_sis540(globals *g, struct pci_dev *dev, const char *name
 	int ret = 0;
 	struct pci_dev *sbdev;
 
-	sbdev = find_southbridge(dev->vendor_id, name);
+	sbdev = find_southbridge(g, dev->vendor_id, name);
 	if (!sbdev)
 		return -1;
 
@@ -744,7 +744,7 @@ static int enable_flash_sb600(globals *g, struct pci_dev *dev, const char *name)
 
 	buses_supported = BUS_LPC | BUS_FWH;
 
-	ret = sb600_probe_spi(dev);
+	ret = sb600_probe_spi(g, dev);
 
 	/* Read ROM strap override register. */
 	OUTB(0x8f, 0xcd6);
@@ -856,7 +856,7 @@ static int enable_flash_sb400(globals *g, struct pci_dev *dev, const char *name)
 	struct pci_dev *smbusdev;
 
 	/* Look for the SMBus device. */
-	smbusdev = pci_dev_find(0x1002, 0x4372);
+	smbusdev = pci_dev_find(g, 0x1002, 0x4372);
 
 	if (!smbusdev) {
 		msg_perr("ERROR: SMBus device not found. Aborting.\n");
@@ -966,7 +966,7 @@ static int enable_flash_mcp6x_7x(globals *g, struct pci_dev *dev, const char *na
 	rpci_write_byte(g, dev, 0x8a, val);
 #endif
 
-	if (mcp6x_spi_init(want_spi))
+	if (mcp6x_spi_init(g, want_spi))
 		ret = 1;
 
 out_msg:
@@ -1246,7 +1246,7 @@ int chipset_flash_enable(globals *g)
 
 	/* Now let's try to find the chipset we have... */
 	for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
-		dev = pci_dev_find(chipset_enables[i].vendor_id,
+		dev = pci_dev_find(g, chipset_enables[i].vendor_id,
 				   chipset_enables[i].device_id);
 		if (!dev)
 			continue;
diff --git a/dummyflasher.c b/dummyflasher.c
index f9caaeb..5e60259 100644
--- a/dummyflasher.c
+++ b/dummyflasher.c
@@ -122,7 +122,7 @@ int dummy_init(globals *g)
 		msg_pdbg("Enabling support for %s flash.\n", "FWH");
 	}
 	if (strstr(bustext, "spi")) {
-		register_spi_programmer(&spi_programmer_dummyflasher);
+		register_spi_programmer(g, &spi_programmer_dummyflasher);
 		msg_pdbg("Enabling support for %s flash.\n", "SPI");
 	}
 	if (buses_supported == BUS_NONE)
diff --git a/ichspi.c b/ichspi.c
index 259e67c..3160a5d 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1194,17 +1194,17 @@ int ich_init_spi(globals *g, struct pci_dev *dev, uint32_t base, void *rcrb,
 
 	switch (ich_generation) {
 	case 7:
-		register_spi_programmer(&spi_programmer_ich7);
+		register_spi_programmer(g, &spi_programmer_ich7);
 		spibar_offset = 0x3020;
 		break;
 	case 8:
-		register_spi_programmer(&spi_programmer_ich9);
+		register_spi_programmer(g, &spi_programmer_ich9);
 		spibar_offset = 0x3020;
 		break;
 	case 9:
 	case 10:
 	default:		/* Future version might behave the same */
-		register_spi_programmer(&spi_programmer_ich9);
+		register_spi_programmer(g, &spi_programmer_ich9);
 		spibar_offset = 0x3800;
 		break;
 	}
@@ -1361,7 +1361,7 @@ int via_init_spi(globals *g, struct pci_dev *dev)
 
 	/* Not sure if it speaks all these bus protocols. */
 	buses_supported = BUS_LPC | BUS_FWH;
-	register_spi_programmer(&spi_programmer_via);
+	register_spi_programmer(g, &spi_programmer_via);
 
 	msg_pdbg("0x00: 0x%04x     (SPIS)\n", mmio_readw(ich_spibar + 0));
 	msg_pdbg("0x02: 0x%04x     (SPIC)\n", mmio_readw(ich_spibar + 2));
diff --git a/internal.c b/internal.c
index b2ca5e4..4dea240 100644
--- a/internal.c
+++ b/internal.c
@@ -24,7 +24,7 @@
 #include "programmer.h"
 
 #if NEED_PCI == 1
-struct pci_dev *pci_dev_find_filter(struct pci_filter filter)
+struct pci_dev *pci_dev_find_filter(globals *g, struct pci_filter filter)
 {
 	struct pci_dev *temp;
 
@@ -35,7 +35,7 @@ struct pci_dev *pci_dev_find_filter(struct pci_filter filter)
 	return NULL;
 }
 
-struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass)
+struct pci_dev *pci_dev_find_vendorclass(globals *g, uint16_t vendor, uint16_t devclass)
 {
 	struct pci_dev *temp;
 	struct pci_filter filter;
@@ -55,7 +55,7 @@ struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass)
 	return NULL;
 }
 
-struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device)
+struct pci_dev *pci_dev_find(globals *g, uint16_t vendor, uint16_t device)
 {
 	struct pci_dev *temp;
 	struct pci_filter filter;
@@ -71,7 +71,7 @@ struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device)
 	return NULL;
 }
 
-struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
+struct pci_dev *pci_card_find(globals *g, uint16_t vendor, uint16_t device,
 			      uint16_t card_vendor, uint16_t card_device)
 {
 	struct pci_dev *temp;
@@ -198,7 +198,7 @@ int internal_init(globals *g)
 	pci_init(pacc);		/* Initialize the PCI library */
 	pci_scan_bus(pacc);	/* We want to get the list of devices */
 
-	if (processor_flash_enable()) {
+	if (processor_flash_enable(g)) {
 		msg_perr("Processor detection/init failed.\n"
 			 "Aborting.\n");
 		return 1;
@@ -213,7 +213,7 @@ int internal_init(globals *g)
 	dmi_init(g);
 
 	/* In case Super I/O probing would cause pretty explosions. */
-	board_handle_before_superio();
+	board_handle_before_superio(g);
 
 	/* Probe for the Super I/O chip and fill global struct superio. */
 	probe_superio(g);
@@ -226,7 +226,7 @@ int internal_init(globals *g)
 #endif
 
 	/* Check laptop whitelist. */
-	board_handle_before_laptop();
+	board_handle_before_laptop(g);
 
 	/* Warn if a non-whitelisted laptop is detected. */
 	if (is_laptop && !laptop_ok) {
@@ -277,7 +277,7 @@ int internal_init(globals *g)
 	init_superio_ite(g);
 #endif
 
-	board_flash_enable(lb_vendor, lb_part);
+	board_flash_enable(g, lb_vendor, lb_part);
 
 	/* Even if chipset init returns an error code, we don't want to abort.
 	 * The error code might have been a warning only.
diff --git a/it85spi.c b/it85spi.c
index 644ec8e..71687a4 100644
--- a/it85spi.c
+++ b/it85spi.c
@@ -299,7 +299,7 @@ int it85xx_spi_init(globals *g, struct superio s)
 			msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
 		/* Really leave FWH enabled? */
 		/* Set this as SPI controller. */
-		register_spi_programmer(&spi_programmer_it85xx);
+		register_spi_programmer(g, &spi_programmer_it85xx);
 	}
 	return ret;
 }
diff --git a/it87spi.c b/it87spi.c
index 2770e3a..ffcf8ce 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -197,7 +197,7 @@ static uint16_t it87spi_probe(globals *g, uint16_t port)
 	if (buses_supported & BUS_SPI)
 		msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
 	/* FIXME: Add the SPI bus or replace the other buses with it? */
-	register_spi_programmer(&spi_programmer_it87xx);
+	register_spi_programmer(g, &spi_programmer_it87xx);
 	return 0;
 }
 
@@ -223,7 +223,7 @@ int init_superio_ite(globals *g)
 			//it85xx_spi_init(superios[i]);
 			break;
 		case 0x8705:
-			ret |= it8705f_write_enable(superios[i].port);
+			ret |= it8705f_write_enable(g, superios[i].port);
 			break;
 		case 0x8716:
 		case 0x8718:
diff --git a/mcp6x_spi.c b/mcp6x_spi.c
index d2c31be..7badce4 100644
--- a/mcp6x_spi.c
+++ b/mcp6x_spi.c
@@ -100,14 +100,14 @@ static const struct bitbang_spi_master bitbang_spi_master_mcp6x = {
 	.release_bus = mcp6x_release_spibus,
 };
 
-int mcp6x_spi_init(int want_spi)
+int mcp6x_spi_init(globals *g, int want_spi)
 {
 	uint16_t status;
 	uint32_t mcp6x_spibaraddr;
 	struct pci_dev *smbusdev;
 
 	/* Look for the SMBus device (SMBus PCI class) */
-	smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
+	smbusdev = pci_dev_find_vendorclass(g, 0x10de, 0x0c05);
 	if (!smbusdev) {
 		if (want_spi) {
 			msg_perr("ERROR: SMBus device not found. Not enabling "
@@ -160,7 +160,7 @@ int mcp6x_spi_init(int want_spi)
 	mcp_gpiostate = status & 0xff;
 
 	/* Zero halfperiod delay. */
-	if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 0)) {
+	if (bitbang_spi_init(g, &bitbang_spi_master_mcp6x, 0)) {
 		/* This should never happen. */
 		msg_perr("MCP6X bitbang SPI master init failed!\n");
 		return 1;
diff --git a/processor_enable.c b/processor_enable.c
index d680f97..d8bea52 100644
--- a/processor_enable.c
+++ b/processor_enable.c
@@ -26,7 +26,7 @@
 
 #if defined(__i386__) || defined(__x86_64__)
 
-int processor_flash_enable(void)
+int processor_flash_enable(globals *g)
 {
 	/* On x86, flash access is not processor specific except on
 	 * AMD Elan SC520, AMD Geode and maybe other SoC-style CPUs.
@@ -81,7 +81,7 @@ static int is_loongson(void)
 }
 #endif
 
-int processor_flash_enable(void)
+int processor_flash_enable(globals *g)
 {
 	/* FIXME: detect loongson on FreeBSD and OpenBSD as well.  */
 #if defined (__MIPSEL__) && defined (__linux)
diff --git a/programmer.h b/programmer.h
index 441cf19..9d78b59 100644
--- a/programmer.h
+++ b/programmer.h
@@ -127,7 +127,7 @@ struct board_pciid_enable {
 
 	int max_rom_decode_parallel;
 	int status;
-	int (*enable) (void); /* May be NULL. */
+	int (*enable) (globals *g); /* May be NULL. */
 };
 
 extern const struct board_pciid_enable board_pciid_enables[];
@@ -181,19 +181,19 @@ void print_supported_pcidevs(const struct pcidev_status *devs);
 /* board_enable.c */
 void w836xx_ext_enter(uint16_t port);
 void w836xx_ext_leave(uint16_t port);
-int it8705f_write_enable(uint8_t port);
+int it8705f_write_enable(globals *g, uint8_t port);
 uint8_t sio_read(uint16_t port, uint8_t reg);
 void sio_write(uint16_t port, uint8_t reg, uint8_t data);
 void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
-void board_handle_before_superio(void);
-void board_handle_before_laptop(void);
-int board_flash_enable(const char *vendor, const char *part);
+void board_handle_before_superio(globals *g);
+void board_handle_before_laptop(globals *g);
+int board_flash_enable(globals *g, const char *vendor, const char *part);
 
 /* chipset_enable.c */
 int chipset_flash_enable(globals *g);
 
 /* processor_enable.c */
-int processor_flash_enable(void);
+int processor_flash_enable(globals *g);
 #endif
 
 /* physmap.c */
@@ -227,10 +227,10 @@ extern int superio_count;
 #define SUPERIO_VENDOR_ITE	0x1
 #endif
 #if NEED_PCI == 1
-struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
-struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass);
-struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
-struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
+struct pci_dev *pci_dev_find_filter(globals *g, struct pci_filter filter);
+struct pci_dev *pci_dev_find_vendorclass(globals *g, uint16_t vendor, uint16_t devclass);
+struct pci_dev *pci_dev_find(globals *g, uint16_t vendor, uint16_t device);
+struct pci_dev *pci_card_find(globals *g, uint16_t vendor, uint16_t device,
 			      uint16_t card_vendor, uint16_t card_device);
 #endif
 void get_io_perms(void);
@@ -419,7 +419,7 @@ int rayer_spi_init(void);
 #endif
 
 /* bitbang_spi.c */
-int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);
+int bitbang_spi_init(globals *g, const struct bitbang_spi_master *master, int halfperiod);
 int bitbang_spi_shutdown(const struct bitbang_spi_master *master);
 
 /* buspirate_spi.c */
@@ -503,7 +503,7 @@ int default_spi_send_command(globals *g, unsigned int writecnt, unsigned int rea
 int default_spi_send_multicommand(globals *g, struct spi_command *cmds);
 int default_spi_read(globals *g, struct flashchip *flash, uint8_t *buf, int start, int len);
 int default_spi_write_256(globals *g, struct flashchip *flash, uint8_t *buf, int start, int len);
-void register_spi_programmer(const struct spi_programmer *programmer);
+void register_spi_programmer(globals *g, const struct spi_programmer *programmer);
 
 /* ichspi.c */
 #if CONFIG_INTERNAL == 1
@@ -522,13 +522,13 @@ void probe_superio_ite(globals *g);
 int init_superio_ite(globals *g);
 
 /* mcp6x_spi.c */
-int mcp6x_spi_init(int want_spi);
+int mcp6x_spi_init(globals *g, int want_spi);
 
 /* sb600spi.c */
-int sb600_probe_spi(struct pci_dev *dev);
+int sb600_probe_spi(globals *g, struct pci_dev *dev);
 
 /* wbsio_spi.c */
-int wbsio_check_for_spi(void);
+int wbsio_check_for_spi(globals *g);
 #endif
 
 /* serprog.c */
diff --git a/sb600spi.c b/sb600spi.c
index bb21373..f487b58 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -202,7 +202,7 @@ static const struct spi_programmer spi_programmer_sb600 = {
 	.write_256 = default_spi_write_256,
 };
 
-int sb600_probe_spi(struct pci_dev *dev)
+int sb600_probe_spi(globals *g, struct pci_dev *dev)
 {
 	struct pci_dev *smbus_dev;
 	uint32_t tmp;
@@ -257,7 +257,7 @@ int sb600_probe_spi(struct pci_dev *dev)
 	msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]);
 
 	/* Look for the SMBus device. */
-	smbus_dev = pci_dev_find(0x1002, 0x4385);
+	smbus_dev = pci_dev_find(g, 0x1002, 0x4385);
 
 	if (!smbus_dev) {
 		msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
@@ -314,7 +314,7 @@ int sb600_probe_spi(struct pci_dev *dev)
 	/* Bring the FIFO to a clean state. */
 	reset_internal_fifo_pointer();
 
-	register_spi_programmer(&spi_programmer_sb600);
+	register_spi_programmer(g, &spi_programmer_sb600);
 	return 0;
 }
 
diff --git a/spi.c b/spi.c
index 5125279..923f2de 100644
--- a/spi.c
+++ b/spi.c
@@ -192,7 +192,7 @@ uint32_t spi_get_valid_read_addr(globals *g)
 	}
 }
 
-void register_spi_programmer(const struct spi_programmer *pgm)
+void register_spi_programmer(globals *g, const struct spi_programmer *pgm)
 {
 	spi_programmer = pgm;
 	buses_supported |= BUS_SPI;
diff --git a/wbsio_spi.c b/wbsio_spi.c
index 0f364de..9685f6c 100644
--- a/wbsio_spi.c
+++ b/wbsio_spi.c
@@ -74,7 +74,7 @@ static const struct spi_programmer spi_programmer_wbsio = {
 	.write_256 = spi_chip_write_1,
 };
 
-int wbsio_check_for_spi(void)
+int wbsio_check_for_spi(globals *g)
 {
 	if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1)))
 		if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2)))
@@ -82,7 +82,7 @@ int wbsio_check_for_spi(void)
 
 	msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
 
-	register_spi_programmer(&spi_programmer_wbsio);
+	register_spi_programmer(g, &spi_programmer_wbsio);
 	msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is "
 		 "1024 kB!\n", __func__);
 	max_rom_decode.spi = 1024 * 1024;
-- 
1.7.6

