>From ef244faf452aba3741d3caa70325d55819a915f1 Mon Sep 17 00:00:00 2001
From: Tadas Slotkus <devtadas@gmail.com>
Date: Sat, 20 Aug 2011 18:11:12 +0300
Subject: [carFl mem 42/65] Globalisation pass 2: register undo functions

This invades globals to register shutdown, undo functions.
Buffer in globals will be used for registering undo functions
to drop mallocs.

Signed-off-by: Tadas Slotkus <devtadas@gmail.com>
---
 chipset_enable.c |  166 +++++++++++++++++++++++++++---------------------------
 dummyflasher.c   |    2 +-
 flash.h          |    2 +-
 flashrom.c       |    2 +-
 hwaccess.c       |   46 ++++++++--------
 ichspi.c         |   48 ++++++++--------
 internal.c       |    4 +-
 it85spi.c        |    2 +-
 pcidev.c         |   22 ++++----
 programmer.h     |   32 +++++-----
 10 files changed, 163 insertions(+), 163 deletions(-)

diff --git a/chipset_enable.c b/chipset_enable.c
index b4ec96b..cd6ad28 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -39,7 +39,7 @@
 
 #if defined(__i386__) || defined(__x86_64__)
 
-static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
+static int enable_flash_ali_m1533(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
 
@@ -49,23 +49,23 @@ static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
 	 */
 	tmp = pci_read_byte(dev, 0x47);
 	tmp |= 0x46;
-	rpci_write_byte(dev, 0x47, tmp);
+	rpci_write_byte(g, dev, 0x47, tmp);
 
 	return 0;
 }
 
-static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
+static int enable_flash_sis85c496(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
 
 	tmp = pci_read_byte(dev, 0xd0);
 	tmp |= 0xf8;
-	rpci_write_byte(dev, 0xd0, tmp);
+	rpci_write_byte(g, dev, 0xd0, tmp);
 
 	return 0;
 }
 
-static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
+static int enable_flash_sis_mapping(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t new, newer;
 
@@ -74,7 +74,7 @@ static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
 	new = pci_read_byte(dev, 0x40);
 	new &= (~0x04); /* No idea why we clear bit 2. */
 	new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
-	rpci_write_byte(dev, 0x40, new);
+	rpci_write_byte(g, dev, 0x40, new);
 	newer = pci_read_byte(dev, 0x40);
 	if (newer != new) {
 		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
@@ -103,7 +103,7 @@ static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
 	return sbdev;
 }
 
-static int enable_flash_sis501(struct pci_dev *dev, const char *name)
+static int enable_flash_sis501(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
 	int ret = 0;
@@ -113,7 +113,7 @@ static int enable_flash_sis501(struct pci_dev *dev, const char *name)
 	if (!sbdev)
 		return -1;
 
-	ret = enable_flash_sis_mapping(sbdev, name);
+	ret = enable_flash_sis_mapping(g, sbdev, name);
 
 	tmp = sio_read(0x22, 0x80);
 	tmp &= (~0x20);
@@ -128,7 +128,7 @@ static int enable_flash_sis501(struct pci_dev *dev, const char *name)
 	return ret;
 }
 
-static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
+static int enable_flash_sis5511(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
 	int ret = 0;
@@ -138,7 +138,7 @@ static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
 	if (!sbdev)
 		return -1;
 
-	ret = enable_flash_sis_mapping(sbdev, name);
+	ret = enable_flash_sis_mapping(g, sbdev, name);
 
 	tmp = sio_read(0x22, 0x50);
 	tmp &= (~0x20);
@@ -148,7 +148,7 @@ static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
 	return ret;
 }
 
-static int enable_flash_sis530(struct pci_dev *dev, const char *name)
+static int enable_flash_sis530(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t new, newer;
 	int ret = 0;
@@ -158,12 +158,12 @@ static int enable_flash_sis530(struct pci_dev *dev, const char *name)
 	if (!sbdev)
 		return -1;
 
-	ret = enable_flash_sis_mapping(sbdev, name);
+	ret = enable_flash_sis_mapping(g, sbdev, name);
 
 	new = pci_read_byte(sbdev, 0x45);
 	new &= (~0x20);
 	new |= 0x4;
-	rpci_write_byte(sbdev, 0x45, new);
+	rpci_write_byte(g, sbdev, 0x45, new);
 	newer = pci_read_byte(sbdev, 0x45);
 	if (newer != new) {
 		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
@@ -175,7 +175,7 @@ static int enable_flash_sis530(struct pci_dev *dev, const char *name)
 	return ret;
 }
 
-static int enable_flash_sis540(struct pci_dev *dev, const char *name)
+static int enable_flash_sis540(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t new, newer;
 	int ret = 0;
@@ -185,12 +185,12 @@ static int enable_flash_sis540(struct pci_dev *dev, const char *name)
 	if (!sbdev)
 		return -1;
 
-	ret = enable_flash_sis_mapping(sbdev, name);
+	ret = enable_flash_sis_mapping(g, sbdev, name);
 
 	new = pci_read_byte(sbdev, 0x45);
 	new &= (~0x80);
 	new |= 0x40;
-	rpci_write_byte(sbdev, 0x45, new);
+	rpci_write_byte(g, sbdev, 0x45, new);
 	newer = pci_read_byte(sbdev, 0x45);
 	if (newer != new) {
 		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
@@ -208,7 +208,7 @@ static int enable_flash_sis540(struct pci_dev *dev, const char *name)
  *   - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
  *   - Order Number: 290562-001
  */
-static int enable_flash_piix4(struct pci_dev *dev, const char *name)
+static int enable_flash_piix4(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint16_t old, new;
 	uint16_t xbcs = 0x4e;	/* X-Bus Chip Select register. */
@@ -238,7 +238,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
 	if (new == old)
 		return 0;
 
-	rpci_write_word(dev, xbcs, new);
+	rpci_write_word(g, dev, xbcs, new);
 
 	if (pci_read_word(dev, xbcs) != new) {
 		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
@@ -253,7 +253,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
  * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
  * http://download.intel.com/design/chipsets/datashts/30701303.pdf
  */
-static int enable_flash_ich(struct pci_dev *dev, const char *name,
+static int enable_flash_ich(globals *g, struct pci_dev *dev, const char *name,
 			    int bios_cntl)
 {
 	uint8_t old, new;
@@ -284,7 +284,7 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name,
 	if (new == old)
 		return 0;
 
-	rpci_write_byte(dev, bios_cntl, new);
+	rpci_write_byte(g, dev, bios_cntl, new);
 
 	if (pci_read_byte(dev, bios_cntl) != new) {
 		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
@@ -295,7 +295,7 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name,
 	return 0;
 }
 
-static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
+static int enable_flash_ich_4e(globals *g, struct pci_dev *dev, const char *name)
 {
 	/*
 	 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
@@ -303,10 +303,10 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
 	 * FB_DEC_EN2.
 	 */
 	buses_supported = BUS_FWH;
-	return enable_flash_ich(dev, name, 0x4e);
+	return enable_flash_ich(g, dev, name, 0x4e);
 }
 
-static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
+static int enable_flash_ich_dc(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint32_t fwh_conf;
 	char *idsel = NULL;
@@ -335,8 +335,8 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
 		msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to "
 			 "0x%012" PRIx64 " for top 16 MB.", fwh_idsel_old,
 			 fwh_idsel);
-		rpci_write_long(dev, 0xd0, (fwh_idsel >> 16) & 0xffffffff);
-		rpci_write_word(dev, 0xd4, fwh_idsel & 0xffff);
+		rpci_write_long(g, dev, 0xd0, (fwh_idsel >> 16) & 0xffffffff);
+		rpci_write_word(g, dev, 0xd4, fwh_idsel & 0xffff);
 		/* FIXME: Decode settings are not changed. */
 	} else if (idsel) {
 		msg_perr("Error: fwh_idsel= specified, but no value given.\n");
@@ -416,15 +416,15 @@ idsel_garbage_out:
 	 * buses_supported anyway.
 	 */
 	buses_supported = BUS_FWH;
-	return enable_flash_ich(dev, name, 0xdc);
+	return enable_flash_ich(g, dev, name, 0xdc);
 }
 
-static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
+static int enable_flash_poulsbo(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint16_t old, new;
 	int err;
 
-	if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
+	if ((err = enable_flash_ich(g, dev, name, 0xd8)) != 0)
 		return err;
 
 	old = pci_read_byte(dev, 0xd9);
@@ -433,7 +433,7 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
 	new = old & ~1;
 
 	if (new != old)
-		rpci_write_byte(dev, 0xd9, new);
+		rpci_write_byte(g, dev, 0xd9, new);
 
 	buses_supported = BUS_FWH;
 	return 0;
@@ -444,13 +444,13 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
 #define ICH_STRAP_PCI  0x02
 #define ICH_STRAP_LPC  0x03
 
-static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
+static int enable_flash_vt8237s_spi(globals *g, struct pci_dev *dev, const char *name)
 {
 	/* Do we really need no write enable? */
-	return via_init_spi(dev);
+	return via_init_spi(g, dev);
 }
 
-static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
+static int enable_flash_ich_dc_spi(globals *g, struct pci_dev *dev, const char *name,
 				   int ich_generation)
 {
 	int ret;
@@ -466,7 +466,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
 	static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
 
 	/* Enable Flash Writes */
-	ret = enable_flash_ich_dc(dev, name);
+	ret = enable_flash_ich_dc(g, dev, name);
 
 	/* Get physical address of Root Complex Register Block */
 	tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
@@ -503,7 +503,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
 	}
 
 	/* This adds BUS_SPI */
-	if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
+	if (ich_init_spi(g, dev, tmp, rcrb, ich_generation) != 0) {
 		if (!ret)
 			ret = ERROR_NONFATAL;
 	}
@@ -511,27 +511,27 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
 	return ret;
 }
 
-static int enable_flash_ich7(struct pci_dev *dev, const char *name)
+static int enable_flash_ich7(globals *g, struct pci_dev *dev, const char *name)
 {
-	return enable_flash_ich_dc_spi(dev, name, 7);
+	return enable_flash_ich_dc_spi(g, dev, name, 7);
 }
 
-static int enable_flash_ich8(struct pci_dev *dev, const char *name)
+static int enable_flash_ich8(globals *g, struct pci_dev *dev, const char *name)
 {
-	return enable_flash_ich_dc_spi(dev, name, 8);
+	return enable_flash_ich_dc_spi(g, dev, name, 8);
 }
 
-static int enable_flash_ich9(struct pci_dev *dev, const char *name)
+static int enable_flash_ich9(globals *g, struct pci_dev *dev, const char *name)
 {
-	return enable_flash_ich_dc_spi(dev, name, 9);
+	return enable_flash_ich_dc_spi(g, dev, name, 9);
 }
 
-static int enable_flash_ich10(struct pci_dev *dev, const char *name)
+static int enable_flash_ich10(globals *g, struct pci_dev *dev, const char *name)
 {
-	return enable_flash_ich_dc_spi(dev, name, 10);
+	return enable_flash_ich_dc_spi(g, dev, name, 10);
 }
 
-static int via_no_byte_merge(struct pci_dev *dev, const char *name)
+static int via_no_byte_merge(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t val;
 
@@ -539,22 +539,22 @@ static int via_no_byte_merge(struct pci_dev *dev, const char *name)
 	if (val & 0x40) {
 		msg_pdbg("Disabling byte merging\n");
 		val &= ~0x40;
-		rpci_write_byte(dev, 0x71, val);
+		rpci_write_byte(g, dev, 0x71, val);
 	}
 	return NOT_DONE_YET;	/* need to find south bridge, too */
 }
 
-static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
+static int enable_flash_vt823x(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t val;
 
 	/* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
-	rpci_write_byte(dev, 0x41, 0x7f);
+	rpci_write_byte(g, dev, 0x41, 0x7f);
 
 	/* ROM write enable */
 	val = pci_read_byte(dev, 0x40);
 	val |= 0x10;
-	rpci_write_byte(dev, 0x40, val);
+	rpci_write_byte(g, dev, 0x40, val);
 
 	if (pci_read_byte(dev, 0x40) != val) {
 		msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
@@ -566,13 +566,13 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
 		/* All memory cycles, not just ROM ones, go to LPC. */
 		val = pci_read_byte(dev, 0x59);
 		val &= ~0x80;
-		rpci_write_byte(dev, 0x59, val);
+		rpci_write_byte(g, dev, 0x59, val);
 	}
 
 	return 0;
 }
 
-static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
+static int enable_flash_cs5530(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t reg8;
 
@@ -600,12 +600,12 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
 	reg8 |= LOWER_ROM_ADDRESS_RANGE;
 	reg8 |= UPPER_ROM_ADDRESS_RANGE;
 	reg8 |= ROM_WRITE_ENABLE;
-	rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
+	rpci_write_byte(g, dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
 
 	/* Set positive decode on ROM. */
 	reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
 	reg8 |= BIOS_ROM_POSITIVE_DECODE;
-	rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
+	rpci_write_byte(g, dev, DECODE_CONTROL_REG2, reg8);
 
 	reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
 	if (reg8 & CS5530_ISA_MASTER) {
@@ -636,7 +636,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
  * To enable write to NOR Boot flash for the benefit of systems that have such
  * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
  */
-static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
+static int enable_flash_cs5536(globals *g, struct pci_dev *dev, const char *name)
 {
 #define MSR_RCONF_DEFAULT	0x1808
 #define MSR_NORF_CTL		0x51400018
@@ -665,11 +665,11 @@ static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
 	return 0;
 }
 
-static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
+static int enable_flash_sc1100(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t new;
 
-	rpci_write_byte(dev, 0x52, 0xee);
+	rpci_write_byte(g, dev, 0x52, 0xee);
 
 	new = pci_read_byte(dev, 0x52);
 
@@ -683,7 +683,7 @@ static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
 }
 
 /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
-static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
+static int enable_flash_amd8111(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t old, new;
 
@@ -691,7 +691,7 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
 	old = pci_read_byte(dev, 0x43);
 	new = old | 0xC0;
 	if (new != old) {
-		rpci_write_byte(dev, 0x43, new);
+		rpci_write_byte(g, dev, 0x43, new);
 		if (pci_read_byte(dev, 0x43) != new) {
 			msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
 				  "(WARNING ONLY).\n", 0x43, new, name);
@@ -703,7 +703,7 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
 	new = old | 0x01;
 	if (new == old)
 		return 0;
-	rpci_write_byte(dev, 0x40, new);
+	rpci_write_byte(g, dev, 0x40, new);
 
 	if (pci_read_byte(dev, 0x40) != new) {
 		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
@@ -714,7 +714,7 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
 	return 0;
 }
 
-static int enable_flash_sb600(struct pci_dev *dev, const char *name)
+static int enable_flash_sb600(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint32_t prot;
 	uint8_t reg;
@@ -732,7 +732,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
 			  (prot & 0xfffff800),
 			  (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
 		prot &= 0xfffffffc;
-		rpci_write_byte(dev, reg, prot);
+		rpci_write_byte(g, dev, reg, prot);
 		prot = pci_read_long(dev, reg);
 		if (prot & 0x3)
 			msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n",
@@ -784,20 +784,20 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
 	return ret;
 }
 
-static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
+static int enable_flash_nvidia_nforce2(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
 
-	rpci_write_byte(dev, 0x92, 0);
+	rpci_write_byte(g, dev, 0x92, 0);
 
 	tmp = pci_read_byte(dev, 0x6d);
 	tmp |= 0x01;
-	rpci_write_byte(dev, 0x6d, tmp);
+	rpci_write_byte(g, dev, 0x6d, tmp);
 
 	return 0;
 }
 
-static int enable_flash_ck804(struct pci_dev *dev, const char *name)
+static int enable_flash_ck804(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t old, new;
 
@@ -810,7 +810,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name)
 	old = pci_read_byte(dev, 0x88);
 	new = old | 0xc0;
 	if (new != old) {
-		rpci_write_byte(dev, 0x88, new);
+		rpci_write_byte(g, dev, 0x88, new);
 		if (pci_read_byte(dev, 0x88) != new) {
 			msg_pinfo("Setting register to set 0x%x to 0x%x on %s "
 				  "failed (WARNING ONLY).\n", 0x88, new, name);
@@ -821,7 +821,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name)
 	new = old | 0x01;
 	if (new == old)
 		return 0;
-	rpci_write_byte(dev, 0x6d, new);
+	rpci_write_byte(g, dev, 0x6d, new);
 
 	if (pci_read_byte(dev, 0x6d) != new) {
 		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
@@ -832,7 +832,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name)
 	return 0;
 }
 
-static int enable_flash_osb4(struct pci_dev *dev, const char *name)
+static int enable_flash_osb4(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
 
@@ -850,7 +850,7 @@ static int enable_flash_osb4(struct pci_dev *dev, const char *name)
 }
 
 /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
-static int enable_flash_sb400(struct pci_dev *dev, const char *name)
+static int enable_flash_sb400(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
 	struct pci_dev *smbusdev;
@@ -866,12 +866,12 @@ static int enable_flash_sb400(struct pci_dev *dev, const char *name)
 	/* Enable some SMBus stuff. */
 	tmp = pci_read_byte(smbusdev, 0x79);
 	tmp |= 0x01;
-	rpci_write_byte(smbusdev, 0x79, tmp);
+	rpci_write_byte(g, smbusdev, 0x79, tmp);
 
 	/* Change southbridge. */
 	tmp = pci_read_byte(dev, 0x48);
 	tmp |= 0x21;
-	rpci_write_byte(dev, 0x48, tmp);
+	rpci_write_byte(g, dev, 0x48, tmp);
 
 	/* Now become a bit silly. */
 	tmp = INB(0xc6f);
@@ -885,7 +885,7 @@ static int enable_flash_sb400(struct pci_dev *dev, const char *name)
 	return 0;
 }
 
-static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
+static int enable_flash_mcp55(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t old, new, val;
 	uint16_t wordval;
@@ -893,19 +893,19 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
 	/* Set the 0-16 MB enable bits. */
 	val = pci_read_byte(dev, 0x88);
 	val |= 0xff;		/* 256K */
-	rpci_write_byte(dev, 0x88, val);
+	rpci_write_byte(g, dev, 0x88, val);
 	val = pci_read_byte(dev, 0x8c);
 	val |= 0xff;		/* 1M */
-	rpci_write_byte(dev, 0x8c, val);
+	rpci_write_byte(g, dev, 0x8c, val);
 	wordval = pci_read_word(dev, 0x90);
 	wordval |= 0x7fff;	/* 16M */
-	rpci_write_word(dev, 0x90, wordval);
+	rpci_write_word(g, dev, 0x90, wordval);
 
 	old = pci_read_byte(dev, 0x6d);
 	new = old | 0x01;
 	if (new == old)
 		return 0;
-	rpci_write_byte(dev, 0x6d, new);
+	rpci_write_byte(g, dev, 0x6d, new);
 
 	if (pci_read_byte(dev, 0x6d) != new) {
 		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
@@ -921,7 +921,7 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
  * It is assumed that LPC chips need the MCP55 code and SPI chips need the
  * code provided in enable_flash_mcp6x_7x_common.
  */
-static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
+static int enable_flash_mcp6x_7x(globals *g, struct pci_dev *dev, const char *name)
 {
 	int ret = 0, want_spi = 0;
 	uint8_t val;
@@ -935,7 +935,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
 
 	switch ((val >> 5) & 0x3) {
 	case 0x0:
-		ret = enable_flash_mcp55(dev, name);
+		ret = enable_flash_mcp55(g, dev, name);
 		buses_supported = BUS_LPC;
 		msg_pdbg("Flash bus type is LPC\n");
 		break;
@@ -963,7 +963,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
 #if 0
 	val |= (1 << 6);
 	val &= ~(1 << 5);
-	rpci_write_byte(dev, 0x8a, val);
+	rpci_write_byte(g, dev, 0x8a, val);
 #endif
 
 	if (mcp6x_spi_init(want_spi))
@@ -979,18 +979,18 @@ out_msg:
 	return ret;
 }
 
-static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
+static int enable_flash_ht1000(globals *g, struct pci_dev *dev, const char *name)
 {
 	uint8_t val;
 
 	/* Set the 4MB enable bit. */
 	val = pci_read_byte(dev, 0x41);
 	val |= 0x0e;
-	rpci_write_byte(dev, 0x41, val);
+	rpci_write_byte(g, dev, 0x41, val);
 
 	val = pci_read_byte(dev, 0x43);
 	val |= (1 << 4);
-	rpci_write_byte(dev, 0x43, val);
+	rpci_write_byte(g, dev, 0x43, val);
 
 	return 0;
 }
@@ -1002,7 +1002,7 @@ static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
  * complete flash is mapped somewhere below 1G. The position can be determined
  * by the BOOTCS PAR register.
  */
-static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
+static int get_flashbase_sc520(globals *g, struct pci_dev *dev, const char *name)
 {
 	int i, bootcs_found = 0;
 	uint32_t parx = 0;
@@ -1237,7 +1237,7 @@ const struct penable chipset_enables[] = {
 	{},
 };
 
-int chipset_flash_enable(void)
+int chipset_flash_enable(globals *g)
 {
 	struct pci_dev *dev = NULL;
 	int ret = -2;		/* Nothing! */
@@ -1277,7 +1277,7 @@ int chipset_flash_enable(void)
 				  "(-V) log. Thank you!\n");
 		}
 		msg_pinfo("Enabling flash write... ");
-		ret = chipset_enables[i].doit(dev,
+		ret = chipset_enables[i].doit(g, dev,
 					      chipset_enables[i].device_name);
 		if (ret == NOT_DONE_YET) {
 			ret = -2;
diff --git a/dummyflasher.c b/dummyflasher.c
index 5354fa9..b7e88ef 100644
--- a/dummyflasher.c
+++ b/dummyflasher.c
@@ -222,7 +222,7 @@ int dummy_init(globals *g)
 #endif
 
 dummy_init_out:
-	if (register_shutdown(dummy_shutdown, NULL)) {
+	if (register_shutdown(g, dummy_shutdown, NULL)) {
 		free(flashchip_contents);
 		return 1;
 	}
diff --git a/flash.h b/flash.h
index becaec8..7b88370 100644
--- a/flash.h
+++ b/flash.h
@@ -41,7 +41,7 @@
 typedef unsigned long chipaddr;
 typedef struct globals globals;
 
-int register_shutdown(int (*function) (void *data), void *data);
+int register_shutdown(globals *g, int (*function) (void *data), void *data);
 void *programmer_map_flash_region(globals *g, const char *descr, unsigned long phys_addr,
 				  size_t len);
 void programmer_unmap_flash_region(globals *g, void *virt_addr, size_t len);
diff --git a/flashrom.c b/flashrom.c
index 084a912..a217954 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -478,7 +478,7 @@ static int check_block_eraser(const struct flashchip *flash, int k, int log);
  * Please note that the first (void *data) belongs to the function signature of
  * the function passed as first parameter.
  */
-int register_shutdown(int (*function) (void *data), void *data)
+int register_shutdown(globals *g, int (*function) (void *data), void *data)
 {
 	if (shutdown_fn_count >= SHUTDOWN_MAXFN) {
 		msg_perr("Tried to register more than %i shutdown functions.\n",
diff --git a/hwaccess.c b/hwaccess.c
index 8c89925..ee7c50c 100644
--- a/hwaccess.c
+++ b/hwaccess.c
@@ -222,7 +222,7 @@ int undo_mmio_write(void *p)
 	return 0;
 }
 
-#define register_undo_mmio_write(a, c)					\
+#define register_undo_mmio_write(g, a, c)					\
 {									\
 	struct undo_mmio_write_data *undo_mmio_write_data;		\
 	undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \
@@ -233,60 +233,60 @@ int undo_mmio_write(void *p)
 	undo_mmio_write_data->addr = a;					\
 	undo_mmio_write_data->type = mmio_write_type_##c;		\
 	undo_mmio_write_data->c##data = mmio_read##c(a);		\
-	register_shutdown(undo_mmio_write, undo_mmio_write_data);	\
+	register_shutdown(g, undo_mmio_write, undo_mmio_write_data);	\
 }
 
-#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b)
-#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w)
-#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l)
+#define register_undo_mmio_writeb(g, a) register_undo_mmio_write(g, a, b)
+#define register_undo_mmio_writew(g, a) register_undo_mmio_write(g, a, w)
+#define register_undo_mmio_writel(g, a) register_undo_mmio_write(g, a, l)
 
-void rmmio_writeb(uint8_t val, void *addr)
+void rmmio_writeb(globals *g, uint8_t val, void *addr)
 {
-	register_undo_mmio_writeb(addr);
+	register_undo_mmio_writeb(g, addr);
 	mmio_writeb(val, addr);
 }
 
-void rmmio_writew(uint16_t val, void *addr)
+void rmmio_writew(globals *g, uint16_t val, void *addr)
 {
-	register_undo_mmio_writew(addr);
+	register_undo_mmio_writew(g, addr);
 	mmio_writew(val, addr);
 }
 
-void rmmio_writel(uint32_t val, void *addr)
+void rmmio_writel(globals *g, uint32_t val, void *addr)
 {
-	register_undo_mmio_writel(addr);
+	register_undo_mmio_writel(g, addr);
 	mmio_writel(val, addr);
 }
 
-void rmmio_le_writeb(uint8_t val, void *addr)
+void rmmio_le_writeb(globals *g, uint8_t val, void *addr)
 {
-	register_undo_mmio_writeb(addr);
+	register_undo_mmio_writeb(g, addr);
 	mmio_le_writeb(val, addr);
 }
 
-void rmmio_le_writew(uint16_t val, void *addr)
+void rmmio_le_writew(globals *g, uint16_t val, void *addr)
 {
-	register_undo_mmio_writew(addr);
+	register_undo_mmio_writew(g, addr);
 	mmio_le_writew(val, addr);
 }
 
-void rmmio_le_writel(uint32_t val, void *addr)
+void rmmio_le_writel(globals *g, uint32_t val, void *addr)
 {
-	register_undo_mmio_writel(addr);
+	register_undo_mmio_writel(g, addr);
 	mmio_le_writel(val, addr);
 }
 
-void rmmio_valb(void *addr)
+void rmmio_valb(globals *g, void *addr)
 {
-	register_undo_mmio_writeb(addr);
+	register_undo_mmio_writeb(g, addr);
 }
 
-void rmmio_valw(void *addr)
+void rmmio_valw(globals *g, void *addr)
 {
-	register_undo_mmio_writew(addr);
+	register_undo_mmio_writew(g, addr);
 }
 
-void rmmio_vall(void *addr)
+void rmmio_vall(globals *g, void *addr)
 {
-	register_undo_mmio_writel(addr);
+	register_undo_mmio_writel(g, addr);
 }
diff --git a/ichspi.c b/ichspi.c
index e16c90d..259e67c 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -217,7 +217,7 @@ static uint16_t REGREAD8(int X)
 static int find_opcode(OPCODES *op, uint8_t opcode);
 static int find_preop(OPCODES *op, uint8_t preop);
 static int generate_opcodes(OPCODES * op);
-static int program_opcodes(OPCODES *op, int enable_undo);
+static int program_opcodes(globals *g, OPCODES *op, int enable_undo);
 static int run_opcode(globals *g, OPCODE op, uint32_t offset,
 		      uint8_t datalength, uint8_t * data);
 
@@ -359,7 +359,7 @@ static uint8_t lookup_spi_type(uint8_t opcode)
 	return 0xFF;
 }
 
-static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
+static int reprogram_opcode_on_the_fly(globals *g, uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
 {
 	uint8_t spi_type;
 
@@ -389,7 +389,7 @@ static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, un
 		int oppos=2;	// use original JEDEC_BE_D8 offset
 		curopcodes->opcode[oppos].opcode = opcode;
 		curopcodes->opcode[oppos].spi_type = spi_type;
-		program_opcodes(curopcodes, 0);
+		program_opcodes(g, curopcodes, 0);
 		oppos = find_opcode(curopcodes, opcode);
 		msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
 		return oppos;
@@ -477,7 +477,7 @@ static int generate_opcodes(OPCODES * op)
 	return 0;
 }
 
-static int program_opcodes(OPCODES *op, int enable_undo)
+static int program_opcodes(globals *g, OPCODES *op, int enable_undo)
 {
 	uint8_t a;
 	uint16_t preop, optype;
@@ -513,10 +513,10 @@ static int program_opcodes(OPCODES *op, int enable_undo)
 	case SPI_CONTROLLER_VIA:
 		/* Register undo only for enable_undo=1, i.e. first call. */
 		if (enable_undo) {
-			rmmio_valw(ich_spibar + ICH7_REG_PREOP);
-			rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
-			rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
-			rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
+			rmmio_valw(g, ich_spibar + ICH7_REG_PREOP);
+			rmmio_valw(g, ich_spibar + ICH7_REG_OPTYPE);
+			rmmio_vall(g, ich_spibar + ICH7_REG_OPMENU);
+			rmmio_vall(g, ich_spibar + ICH7_REG_OPMENU + 4);
 		}
 		mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
 		mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
@@ -526,10 +526,10 @@ static int program_opcodes(OPCODES *op, int enable_undo)
 	case SPI_CONTROLLER_ICH9:
 		/* Register undo only for enable_undo=1, i.e. first call. */
 		if (enable_undo) {
-			rmmio_valw(ich_spibar + ICH9_REG_PREOP);
-			rmmio_valw(ich_spibar + ICH9_REG_OPTYPE);
-			rmmio_vall(ich_spibar + ICH9_REG_OPMENU);
-			rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4);
+			rmmio_valw(g, ich_spibar + ICH9_REG_PREOP);
+			rmmio_valw(g, ich_spibar + ICH9_REG_OPTYPE);
+			rmmio_vall(g, ich_spibar + ICH9_REG_OPMENU);
+			rmmio_vall(g, ich_spibar + ICH9_REG_OPMENU + 4);
 		}
 		mmio_writew(preop, ich_spibar + ICH9_REG_PREOP);
 		mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE);
@@ -548,7 +548,7 @@ static int program_opcodes(OPCODES *op, int enable_undo)
  * Try to set BBAR (BIOS Base Address Register), but read back the value in case
  * it didn't stick.
  */
-static void ich_set_bbar(uint32_t min_addr)
+static void ich_set_bbar(globals *g, uint32_t min_addr)
 {
 	int bbar_off;
 	switch (spi_programmer->type) {
@@ -571,7 +571,7 @@ static void ich_set_bbar(uint32_t min_addr)
 	}
 	min_addr &= BBAR_MASK;
 	ichspi_bbar |= min_addr;
-	rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
+	rmmio_writel(g, ichspi_bbar, ich_spibar + bbar_off);
 	ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
 
 	/* We don't have any option except complaining. And if the write
@@ -631,7 +631,7 @@ static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
  *
  * It should be called before ICH sends any spi command.
  */
-static int ich_init_opcodes(void)
+static int ich_init_opcodes(globals *g)
 {
 	int rc = 0;
 	OPCODES *curopcodes_done;
@@ -646,12 +646,12 @@ static int ich_init_opcodes(void)
 	} else {
 		msg_pdbg("Programming OPCODES... ");
 		curopcodes_done = &O_ST_M25P;
-		rc = program_opcodes(curopcodes_done, 1);
+		rc = program_opcodes(g, curopcodes_done, 1);
 		/* Technically not part of opcode init, but it allows opcodes
 		 * to run without transaction errors by setting the lowest
 		 * allowed address to zero.
 		 */
-		ich_set_bbar(0);
+		ich_set_bbar(g, 0);
 	}
 
 	if (rc) {
@@ -955,7 +955,7 @@ static int ich_spi_send_command(globals *g, unsigned int writecnt, unsigned int
 	opcode_index = find_opcode(curopcodes, cmd);
 	if (opcode_index == -1) {
 		if (!ichspi_lock)
-			opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
+			opcode_index = reprogram_opcode_on_the_fly(g, cmd, writecnt, readcnt);
 		if (opcode_index == -1) {
 			msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
 				 cmd);
@@ -1097,7 +1097,7 @@ static int ich_spi_send_multicommand(globals *g, struct spi_command *cmds)
 				 * No need to bother with fixups.
 				 */
 				if (!ichspi_lock) {
-					oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
+					oppos = reprogram_opcode_on_the_fly(g, (cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
 					if (oppos == -1)
 						continue;
 					curopcodes->opcode[oppos].atomic = preoppos + 1;
@@ -1184,7 +1184,7 @@ static const struct spi_programmer spi_programmer_ich9 = {
 	.write_256 = default_spi_write_256,
 };
 
-int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
+int ich_init_spi(globals *g, struct pci_dev *dev, uint32_t base, void *rcrb,
 			int ich_generation)
 {
 	int i;
@@ -1252,7 +1252,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 			msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
 			ichspi_lock = 1;
 		}
-		ich_init_opcodes();
+		ich_init_opcodes(g);
 		break;
 	case SPI_CONTROLLER_ICH9:
 		tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
@@ -1315,7 +1315,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 		tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
 		msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
 
-		ich_init_opcodes();
+		ich_init_opcodes(g);
 		break;
 	default:
 		/* Nothing */
@@ -1350,7 +1350,7 @@ static const struct spi_programmer spi_programmer_via = {
 	.write_256 = default_spi_write_256,
 };
 
-int via_init_spi(struct pci_dev *dev)
+int via_init_spi(globals *g, struct pci_dev *dev)
 {
 	uint32_t mmio_base;
 	int i;
@@ -1393,7 +1393,7 @@ int via_init_spi(struct pci_dev *dev)
 		ichspi_lock = 1;
 	}
 
-	ich_init_opcodes();
+	ich_init_opcodes(g);
 
 	return 0;
 }
diff --git a/internal.c b/internal.c
index cf899f3..4d9e416 100644
--- a/internal.c
+++ b/internal.c
@@ -184,7 +184,7 @@ int internal_init(globals *g)
 	free(arg);
 
 	get_io_perms();
-	if (register_shutdown(internal_shutdown, NULL))
+	if (register_shutdown(g, internal_shutdown, NULL))
 		return 1;
 
 	/* Default to Parallel/LPC/FWH flash devices. If a known host controller
@@ -264,7 +264,7 @@ int internal_init(globals *g)
 	/* try to enable it. Failure IS an option, since not all motherboards
 	 * really need this to be done, etc., etc.
 	 */
-	ret = chipset_flash_enable();
+	ret = chipset_flash_enable(g);
 	if (ret == -2) {
 		msg_perr("WARNING: No chipset found. Flash detection "
 			 "will most likely fail.\n");
diff --git a/it85spi.c b/it85spi.c
index 739e4f4..644ec8e 100644
--- a/it85spi.c
+++ b/it85spi.c
@@ -234,7 +234,7 @@ static int it85xx_spi_common_init(globals *g, struct superio s)
 	msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__,
 	         s.vendor);
 
-	if (register_shutdown(it85xx_shutdown, (void *)g))
+	if (register_shutdown(g, it85xx_shutdown, (void *)g))
 		return 1;
 
 #ifdef LPC_IO
diff --git a/pcidev.c b/pcidev.c
index e8b4dc1..116b0ef 100644
--- a/pcidev.c
+++ b/pcidev.c
@@ -291,7 +291,7 @@ int undo_pci_write(void *p)
 	return 0;
 }
 
-#define register_undo_pci_write(a, b, c) 				\
+#define register_undo_pci_write(g, a, b, c) 				\
 {									\
 	struct undo_pci_write_data *undo_pci_write_data;		\
 	undo_pci_write_data = malloc(sizeof(struct undo_pci_write_data)); \
@@ -303,27 +303,27 @@ int undo_pci_write(void *p)
 	undo_pci_write_data->reg = b;					\
 	undo_pci_write_data->type = pci_write_type_##c;			\
 	undo_pci_write_data->c##data = pci_read_##c(dev, reg);		\
-	register_shutdown(undo_pci_write, undo_pci_write_data);		\
+	register_shutdown(g, undo_pci_write, undo_pci_write_data);		\
 }
 
-#define register_undo_pci_write_byte(a, b) register_undo_pci_write(a, b, byte)
-#define register_undo_pci_write_word(a, b) register_undo_pci_write(a, b, word)
-#define register_undo_pci_write_long(a, b) register_undo_pci_write(a, b, long)
+#define register_undo_pci_write_byte(g, a, b) register_undo_pci_write(g, a, b, byte)
+#define register_undo_pci_write_word(g, a, b) register_undo_pci_write(g, a, b, word)
+#define register_undo_pci_write_long(g, a, b) register_undo_pci_write(g, a, b, long)
 
-int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data)
+int rpci_write_byte(globals *g, struct pci_dev *dev, int reg, uint8_t data)
 {
-	register_undo_pci_write_byte(dev, reg);
+	register_undo_pci_write_byte(g, dev, reg);
 	return pci_write_byte(dev, reg, data);
 }
  
-int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data)
+int rpci_write_word(globals *g, struct pci_dev *dev, int reg, uint16_t data)
 {
-	register_undo_pci_write_word(dev, reg);
+	register_undo_pci_write_word(g, dev, reg);
 	return pci_write_word(dev, reg, data);
 }
  
-int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data)
+int rpci_write_long(globals *g, struct pci_dev *dev, int reg, uint32_t data)
 {
-	register_undo_pci_write_long(dev, reg);
+	register_undo_pci_write_long(g, dev, reg);
 	return pci_write_long(dev, reg, data);
 }
diff --git a/programmer.h b/programmer.h
index ec9c471..abebf68 100644
--- a/programmer.h
+++ b/programmer.h
@@ -147,7 +147,7 @@ struct penable {
 	int status; /* OK=0 and NT=1 are defines only. Beware! */
 	const char *vendor_name;
 	const char *device_name;
-	int (*doit) (struct pci_dev *dev, const char *name);
+	int (*doit) (globals *g, struct pci_dev *dev, const char *name);
 };
 
 extern const struct penable chipset_enables[];
@@ -228,9 +228,9 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs);
 /* rpci_write_* are reversible writes. The original PCI config space register
  * contents will be restored on shutdown.
  */
-int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);
-int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);
-int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
+int rpci_write_byte(globals *g, struct pci_dev *dev, int reg, uint8_t data);
+int rpci_write_word(globals *g, struct pci_dev *dev, int reg, uint16_t data);
+int rpci_write_long(globals *g, struct pci_dev *dev, int reg, uint32_t data);
 #endif
 
 /* print.c */
@@ -251,7 +251,7 @@ void board_handle_before_laptop(void);
 int board_flash_enable(const char *vendor, const char *part);
 
 /* chipset_enable.c */
-int chipset_flash_enable(void);
+int chipset_flash_enable(globals *g);
 
 /* processor_enable.c */
 int processor_flash_enable(void);
@@ -332,18 +332,18 @@ uint32_t mmio_le_readl(void *addr);
 #define pci_mmio_readb mmio_le_readb
 #define pci_mmio_readw mmio_le_readw
 #define pci_mmio_readl mmio_le_readl
-void rmmio_writeb(uint8_t val, void *addr);
-void rmmio_writew(uint16_t val, void *addr);
-void rmmio_writel(uint32_t val, void *addr);
-void rmmio_le_writeb(uint8_t val, void *addr);
-void rmmio_le_writew(uint16_t val, void *addr);
-void rmmio_le_writel(uint32_t val, void *addr);
+void rmmio_writeb(globals *g, uint8_t val, void *addr);
+void rmmio_writew(globals *g, uint16_t val, void *addr);
+void rmmio_writel(globals *g, uint32_t val, void *addr);
+void rmmio_le_writeb(globals *g, uint8_t val, void *addr);
+void rmmio_le_writew(globals *g, uint16_t val, void *addr);
+void rmmio_le_writel(globals *g, uint32_t val, void *addr);
 #define pci_rmmio_writeb rmmio_le_writeb
 #define pci_rmmio_writew rmmio_le_writew
 #define pci_rmmio_writel rmmio_le_writel
-void rmmio_valb(void *addr);
-void rmmio_valw(void *addr);
-void rmmio_vall(void *addr);
+void rmmio_valb(globals *g, void *addr);
+void rmmio_valw(globals *g, void *addr);
+void rmmio_vall(globals *g, void *addr);
 
 /* programmer.c */
 int noop_shutdown(void);
@@ -569,9 +569,9 @@ void register_spi_programmer(const struct spi_programmer *programmer);
 /* ichspi.c */
 #if CONFIG_INTERNAL == 1
 extern uint32_t ichspi_bbar;
-int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
+int ich_init_spi(globals *g, struct pci_dev *dev, uint32_t base, void *rcrb,
 		    int ich_generation);
-int via_init_spi(struct pci_dev *dev);
+int via_init_spi(globals *g, struct pci_dev *dev);
 
 /* it85spi.c */
 int it85xx_spi_init(globals *g, struct superio s);
-- 
1.7.6

