>From 39b417aa6a42e3064bc2f2f1029f27e5c67eca25 Mon Sep 17 00:00:00 2001
From: Tadas Slotkus <devtadas@gmail.com>
Date: Fri, 19 Aug 2011 15:23:20 +0300
Subject: [carFl mem 26/65] Globalisation pass 1: spi25.c

This commit breaks builds until "Globalistation pass 1: fixes".

It does nothing more, just passes globals structure across function
calls.

Signed-off-by: Tadas Slotkus <devtadas@gmail.com>
---
 spi25.c |  216 +++++++++++++++++++++++++++++++-------------------------------
 1 files changed, 108 insertions(+), 108 deletions(-)

diff --git a/spi25.c b/spi25.c
index 937ee5d..69c3487 100644
--- a/spi25.c
+++ b/spi25.c
@@ -29,13 +29,13 @@
 #include "programmer.h"
 #include "spi.h"
 
-static int spi_rdid(unsigned char *readarr, int bytes)
+static int spi_rdid(globals *g, unsigned char *readarr, int bytes)
 {
 	static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
 	int ret;
 	int i;
 
-	ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
+	ret = spi_send_command(g, sizeof(cmd), bytes, cmd, readarr);
 	if (ret)
 		return ret;
 	msg_cspew("RDID returned");
@@ -45,20 +45,20 @@ static int spi_rdid(unsigned char *readarr, int bytes)
 	return 0;
 }
 
-static int spi_rems(unsigned char *readarr)
+static int spi_rems(globals *g, unsigned char *readarr)
 {
 	unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
 	uint32_t readaddr;
 	int ret;
 
-	ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
+	ret = spi_send_command(g, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
 	if (ret == SPI_INVALID_ADDRESS) {
 		/* Find the lowest even address allowed for reads. */
 		readaddr = (spi_get_valid_read_addr() + 1) & ~1;
 		cmd[1] = (readaddr >> 16) & 0xff,
 		cmd[2] = (readaddr >> 8) & 0xff,
 		cmd[3] = (readaddr >> 0) & 0xff,
-		ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
+		ret = spi_send_command(g, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
 	}
 	if (ret)
 		return ret;
@@ -66,21 +66,21 @@ static int spi_rems(unsigned char *readarr)
 	return 0;
 }
 
-static int spi_res(unsigned char *readarr, int bytes)
+static int spi_res(globals *g, unsigned char *readarr, int bytes)
 {
 	unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
 	uint32_t readaddr;
 	int ret;
 	int i;
 
-	ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
+	ret = spi_send_command(g, sizeof(cmd), bytes, cmd, readarr);
 	if (ret == SPI_INVALID_ADDRESS) {
 		/* Find the lowest even address allowed for reads. */
 		readaddr = (spi_get_valid_read_addr() + 1) & ~1;
 		cmd[1] = (readaddr >> 16) & 0xff,
 		cmd[2] = (readaddr >> 8) & 0xff,
 		cmd[3] = (readaddr >> 0) & 0xff,
-		ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
+		ret = spi_send_command(g, sizeof(cmd), bytes, cmd, readarr);
 	}
 	if (ret)
 		return ret;
@@ -91,13 +91,13 @@ static int spi_res(unsigned char *readarr, int bytes)
 	return 0;
 }
 
-int spi_write_enable(void)
+int spi_write_enable(globals *g)
 {
 	static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
 	int result;
 
 	/* Send WREN (Write Enable) */
-	result = spi_send_command(sizeof(cmd), 0, cmd, NULL);
+	result = spi_send_command(g, sizeof(cmd), 0, cmd, NULL);
 
 	if (result)
 		msg_cerr("%s failed\n", __func__);
@@ -105,21 +105,21 @@ int spi_write_enable(void)
 	return result;
 }
 
-int spi_write_disable(void)
+int spi_write_disable(globals *g)
 {
 	static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
 
 	/* Send WRDI (Write Disable) */
-	return spi_send_command(sizeof(cmd), 0, cmd, NULL);
+	return spi_send_command(g, sizeof(cmd), 0, cmd, NULL);
 }
 
-static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
+static int probe_spi_rdid_generic(globals *g, struct flashchip *flash, int bytes)
 {
 	unsigned char readarr[4];
 	uint32_t id1;
 	uint32_t id2;
 
-	if (spi_rdid(readarr, bytes)) {
+	if (spi_rdid(g, readarr, bytes)) {
 		msg_cdbg("\n");
 		return 0;
 	}
@@ -150,7 +150,7 @@ static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
 		/* Print the status register to tell the
 		 * user about possible write protection.
 		 */
-		spi_prettyprint_status_register(flash);
+		spi_prettyprint_status_register(g, flash);
 
 		return 1;
 	}
@@ -168,12 +168,12 @@ static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
 	return 0;
 }
 
-int probe_spi_rdid(struct flashchip *flash)
+int probe_spi_rdid(globals *g, struct flashchip *flash)
 {
-	return probe_spi_rdid_generic(flash, 3);
+	return probe_spi_rdid_generic(g, flash, 3);
 }
 
-int probe_spi_rdid4(struct flashchip *flash)
+int probe_spi_rdid4(globals *g, struct flashchip *flash)
 {
 	/* Some SPI controllers do not support commands with writecnt=1 and
 	 * readcnt=4.
@@ -189,18 +189,18 @@ int probe_spi_rdid4(struct flashchip *flash)
 #endif
 #endif
 	default:
-		return probe_spi_rdid_generic(flash, 4);
+		return probe_spi_rdid_generic(g, flash, 4);
 	}
 
 	return 0;
 }
 
-int probe_spi_rems(struct flashchip *flash)
+int probe_spi_rems(globals *g, struct flashchip *flash)
 {
 	unsigned char readarr[JEDEC_REMS_INSIZE];
 	uint32_t id1, id2;
 
-	if (spi_rems(readarr)) {
+	if (spi_rems(g, readarr)) {
 		msg_cdbg("\n");
 		return 0;
 	}
@@ -214,7 +214,7 @@ int probe_spi_rems(struct flashchip *flash)
 		/* Print the status register to tell the
 		 * user about possible write protection.
 		 */
-		spi_prettyprint_status_register(flash);
+		spi_prettyprint_status_register(g, flash);
 
 		return 1;
 	}
@@ -232,7 +232,7 @@ int probe_spi_rems(struct flashchip *flash)
 	return 0;
 }
 
-int probe_spi_res1(struct flashchip *flash)
+int probe_spi_res1(globals *g, struct flashchip *flash)
 {
 	static const unsigned char allff[] = {0xff, 0xff, 0xff};
 	static const unsigned char all00[] = {0x00, 0x00, 0x00};
@@ -244,7 +244,7 @@ int probe_spi_res1(struct flashchip *flash)
 	/* Check if RDID is usable and does not return 0xff 0xff 0xff or
 	 * 0x00 0x00 0x00. In that case, RES is pointless.
 	 */
-	if (!spi_rdid(readarr, 3) && memcmp(readarr, allff, 3) &&
+	if (!spi_rdid(g, readarr, 3) && memcmp(readarr, allff, 3) &&
 	    memcmp(readarr, all00, 3)) {
 		msg_cdbg("Ignoring RES in favour of RDID.\n");
 		return 0;
@@ -252,13 +252,13 @@ int probe_spi_res1(struct flashchip *flash)
 	/* Check if REMS is usable and does not return 0xff 0xff or
 	 * 0x00 0x00. In that case, RES is pointless.
 	 */
-	if (!spi_rems(readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
+	if (!spi_rems(g, readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
 	    memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {
 		msg_cdbg("Ignoring RES in favour of REMS.\n");
 		return 0;
 	}
 
-	if (spi_res(readarr, 1)) {
+	if (spi_res(g, readarr, 1)) {
 		msg_cdbg("\n");
 		return 0;
 	}
@@ -273,16 +273,16 @@ int probe_spi_res1(struct flashchip *flash)
 	/* Print the status register to tell the
 	 * user about possible write protection.
 	 */
-	spi_prettyprint_status_register(flash);
+	spi_prettyprint_status_register(g, flash);
 	return 1;
 }
 
-int probe_spi_res2(struct flashchip *flash)
+int probe_spi_res2(globals *g, struct flashchip *flash)
 {
 	unsigned char readarr[2];
 	uint32_t id1, id2;
 
-	if (spi_res(readarr, 2)) {
+	if (spi_res(g, readarr, 2)) {
 		msg_cdbg("\n");
 		return 0;
 	}
@@ -298,11 +298,11 @@ int probe_spi_res2(struct flashchip *flash)
 	/* Print the status register to tell the
 	 * user about possible write protection.
 	 */
-	spi_prettyprint_status_register(flash);
+	spi_prettyprint_status_register(g, flash);
 	return 1;
 }
 
-uint8_t spi_read_status_register(void)
+uint8_t spi_read_status_register(globals *g)
 {
 	static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
 	/* FIXME: No workarounds for driver/hardware bugs in generic code. */
@@ -310,7 +310,7 @@ uint8_t spi_read_status_register(void)
 	int ret;
 
 	/* Read Status Register */
-	ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
+	ret = spi_send_command(g, sizeof(cmd), sizeof(readarr), cmd, readarr);
 	if (ret)
 		msg_cerr("RDSR failed!\n");
 
@@ -414,11 +414,11 @@ void spi_prettyprint_status_register_sst25vf040b(uint8_t status)
 		bpt[(status & 0x1c) >> 2]);
 }
 
-int spi_prettyprint_status_register(struct flashchip *flash)
+int spi_prettyprint_status_register(globals *g, struct flashchip *flash)
 {
 	uint8_t status;
 
-	status = spi_read_status_register();
+	status = spi_read_status_register(g);
 	msg_cdbg("Chip status register is %02x\n", status);
 	switch (flash->manufacture_id) {
 	case ST_ID:
@@ -448,7 +448,7 @@ int spi_prettyprint_status_register(struct flashchip *flash)
 	return 0;
 }
 
-int spi_chip_erase_60(struct flashchip *flash)
+int spi_chip_erase_60(globals *g, struct flashchip *flash)
 {
 	int result;
 	struct spi_command cmds[] = {
@@ -469,7 +469,7 @@ int spi_chip_erase_60(struct flashchip *flash)
 		.readarr	= NULL,
 	}};
 	
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution\n",
 			__func__);
@@ -479,13 +479,13 @@ int spi_chip_erase_60(struct flashchip *flash)
 	 * This usually takes 1-85 s, so wait in 1 s steps.
 	 */
 	/* FIXME: We assume spi_read_status_register will never fail. */
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-		programmer_delay(1000 * 1000);
+	while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+		programmer_delay(g, 1000 * 1000);
 	/* FIXME: Check the status register for errors. */
 	return 0;
 }
 
-int spi_chip_erase_c7(struct flashchip *flash)
+int spi_chip_erase_c7(globals *g, struct flashchip *flash)
 {
 	int result;
 	struct spi_command cmds[] = {
@@ -506,7 +506,7 @@ int spi_chip_erase_c7(struct flashchip *flash)
 		.readarr	= NULL,
 	}};
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution\n", __func__);
 		return result;
@@ -515,13 +515,13 @@ int spi_chip_erase_c7(struct flashchip *flash)
 	 * This usually takes 1-85 s, so wait in 1 s steps.
 	 */
 	/* FIXME: We assume spi_read_status_register will never fail. */
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-		programmer_delay(1000 * 1000);
+	while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+		programmer_delay(g, 1000 * 1000);
 	/* FIXME: Check the status register for errors. */
 	return 0;
 }
 
-int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+int spi_block_erase_52(globals *g, struct flashchip *flash, unsigned int addr, unsigned int blocklen)
 {
 	int result;
 	struct spi_command cmds[] = {
@@ -547,7 +547,7 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int
 		.readarr	= NULL,
 	}};
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution at address 0x%x\n",
 			__func__, addr);
@@ -556,8 +556,8 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int
 	/* Wait until the Write-In-Progress bit is cleared.
 	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
 	 */
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-		programmer_delay(100 * 1000);
+	while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+		programmer_delay(g, 100 * 1000);
 	/* FIXME: Check the status register for errors. */
 	return 0;
 }
@@ -567,7 +567,7 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int
  * 32k for SST
  * 4-32k non-uniform for EON
  */
-int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+int spi_block_erase_d8(globals *g, struct flashchip *flash, unsigned int addr, unsigned int blocklen)
 {
 	int result;
 	struct spi_command cmds[] = {
@@ -593,7 +593,7 @@ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int
 		.readarr	= NULL,
 	}};
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution at address 0x%x\n",
 			__func__, addr);
@@ -602,8 +602,8 @@ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int
 	/* Wait until the Write-In-Progress bit is cleared.
 	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
 	 */
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-		programmer_delay(100 * 1000);
+	while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+		programmer_delay(g, 100 * 1000);
 	/* FIXME: Check the status register for errors. */
 	return 0;
 }
@@ -611,7 +611,7 @@ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int
 /* Block size is usually
  * 4k for PMC
  */
-int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+int spi_block_erase_d7(globals *g, struct flashchip *flash, unsigned int addr, unsigned int blocklen)
 {
 	int result;
 	struct spi_command cmds[] = {
@@ -637,7 +637,7 @@ int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int
 		.readarr	= NULL,
 	}};
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution at address 0x%x\n",
 			__func__, addr);
@@ -646,14 +646,14 @@ int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int
 	/* Wait until the Write-In-Progress bit is cleared.
 	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
 	 */
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-		programmer_delay(100 * 1000);
+	while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+		programmer_delay(g, 100 * 1000);
 	/* FIXME: Check the status register for errors. */
 	return 0;
 }
 
 /* Sector size is usually 4k, though Macronix eliteflash has 64k */
-int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+int spi_block_erase_20(globals *g, struct flashchip *flash, unsigned int addr, unsigned int blocklen)
 {
 	int result;
 	struct spi_command cmds[] = {
@@ -679,7 +679,7 @@ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int
 		.readarr	= NULL,
 	}};
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution at address 0x%x\n",
 			__func__, addr);
@@ -688,39 +688,39 @@ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int
 	/* Wait until the Write-In-Progress bit is cleared.
 	 * This usually takes 15-800 ms, so wait in 10 ms steps.
 	 */
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-		programmer_delay(10 * 1000);
+	while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+		programmer_delay(g, 10 * 1000);
 	/* FIXME: Check the status register for errors. */
 	return 0;
 }
 
-int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+int spi_block_erase_60(globals *g, struct flashchip *flash, unsigned int addr, unsigned int blocklen)
 {
 	if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
 		msg_cerr("%s called with incorrect arguments\n",
 			__func__);
 		return -1;
 	}
-	return spi_chip_erase_60(flash);
+	return spi_chip_erase_60(g, flash);
 }
 
-int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+int spi_block_erase_c7(globals *g, struct flashchip *flash, unsigned int addr, unsigned int blocklen)
 {
 	if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
 		msg_cerr("%s called with incorrect arguments\n",
 			__func__);
 		return -1;
 	}
-	return spi_chip_erase_c7(flash);
+	return spi_chip_erase_c7(g, flash);
 }
 
-int spi_write_status_enable(void)
+int spi_write_status_enable(globals *g)
 {
 	static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
 	int result;
 
 	/* Send EWSR (Enable Write Status Register). */
-	result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
+	result = spi_send_command(g, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
 
 	if (result)
 		msg_cerr("%s failed\n", __func__);
@@ -732,7 +732,7 @@ int spi_write_status_enable(void)
  * This is according the SST25VF016 datasheet, who knows it is more
  * generic that this...
  */
-static int spi_write_status_register_ewsr(struct flashchip *flash, int status)
+static int spi_write_status_register_ewsr(globals *g, struct flashchip *flash, int status)
 {
 	int result;
 	int i = 0;
@@ -755,7 +755,7 @@ static int spi_write_status_register_ewsr(struct flashchip *flash, int status)
 		.readarr	= NULL,
 	}};
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution\n",
 			__func__);
@@ -769,18 +769,18 @@ static int spi_write_status_register_ewsr(struct flashchip *flash, int status)
 	 * allow running RDSR only once. Therefore pick an initial delay of
 	 * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
 	 */
-	programmer_delay(100 * 1000);
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) {
+	programmer_delay(g, 100 * 1000);
+	while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP) {
 		if (++i > 490) {
 			msg_cerr("Error: WIP bit after WRSR never cleared\n");
 			return TIMEOUT_ERROR;
 		}
-		programmer_delay(10 * 1000);
+		programmer_delay(g, 10 * 1000);
 	}
 	return 0;
 }
 
-static int spi_write_status_register_wren(struct flashchip *flash, int status)
+static int spi_write_status_register_wren(globals *g, struct flashchip *flash, int status)
 {
 	int result;
 	int i = 0;
@@ -803,7 +803,7 @@ static int spi_write_status_register_wren(struct flashchip *flash, int status)
 		.readarr	= NULL,
 	}};
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution\n",
 			__func__);
@@ -817,18 +817,18 @@ static int spi_write_status_register_wren(struct flashchip *flash, int status)
 	 * allow running RDSR only once. Therefore pick an initial delay of
 	 * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
 	 */
-	programmer_delay(100 * 1000);
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) {
+	programmer_delay(g, 100 * 1000);
+	while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP) {
 		if (++i > 490) {
 			msg_cerr("Error: WIP bit after WRSR never cleared\n");
 			return TIMEOUT_ERROR;
 		}
-		programmer_delay(10 * 1000);
+		programmer_delay(g, 10 * 1000);
 	}
 	return 0;
 }
 
-int spi_write_status_register(struct flashchip *flash, int status)
+int spi_write_status_register(globals *g, struct flashchip *flash, int status)
 {
 	int ret = 1;
 
@@ -838,13 +838,13 @@ int spi_write_status_register(struct flashchip *flash, int status)
 		flash->feature_bits |= FEATURE_WRSR_EWSR;
 	}
 	if (flash->feature_bits & FEATURE_WRSR_WREN)
-		ret = spi_write_status_register_wren(flash, status);
+		ret = spi_write_status_register_wren(g, flash, status);
 	if (ret && (flash->feature_bits & FEATURE_WRSR_EWSR))
-		ret = spi_write_status_register_ewsr(flash, status);
+		ret = spi_write_status_register_ewsr(g, flash, status);
 	return ret;
 }
 
-int spi_byte_program(int addr, uint8_t databyte)
+int spi_byte_program(globals *g, int addr, uint8_t databyte)
 {
 	int result;
 	struct spi_command cmds[] = {
@@ -871,7 +871,7 @@ int spi_byte_program(int addr, uint8_t databyte)
 		.readarr	= NULL,
 	}};
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution at address 0x%x\n",
 			__func__, addr);
@@ -879,7 +879,7 @@ int spi_byte_program(int addr, uint8_t databyte)
 	return result;
 }
 
-int spi_nbyte_program(int addr, uint8_t *bytes, int len)
+int spi_nbyte_program(globals *g, int addr, uint8_t *bytes, int len)
 {
 	int result;
 	/* FIXME: Switch to malloc based on len unless that kills speed. */
@@ -918,7 +918,7 @@ int spi_nbyte_program(int addr, uint8_t *bytes, int len)
 
 	memcpy(&cmd[4], bytes, len);
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during command execution at address 0x%x\n",
 			__func__, addr);
@@ -930,23 +930,23 @@ int spi_nbyte_program(int addr, uint8_t *bytes, int len)
  * Write 0x00 to the status register. Check if any locks are still set (that
  * part is chip specific). Repeat once.
  */
-int spi_disable_blockprotect(struct flashchip *flash)
+int spi_disable_blockprotect(globals *g, struct flashchip *flash)
 {
 	uint8_t status;
 	int result;
 
-	status = spi_read_status_register();
+	status = spi_read_status_register(g);
 	/* If block protection is disabled, stop here. */
 	if ((status & 0x3c) == 0)
 		return 0;
 
 	msg_cdbg("Some block protection in effect, disabling\n");
-	result = spi_write_status_register(flash, status & ~0x3c);
+	result = spi_write_status_register(g, flash, status & ~0x3c);
 	if (result) {
 		msg_cerr("spi_write_status_register failed\n");
 		return result;
 	}
-	status = spi_read_status_register();
+	status = spi_read_status_register(g);
 	if ((status & 0x3c) != 0) {
 		msg_cerr("Block protection could not be disabled!\n");
 		return 1;
@@ -954,7 +954,7 @@ int spi_disable_blockprotect(struct flashchip *flash)
 	return 0;
 }
 
-int spi_nbyte_read(int address, uint8_t *bytes, int len)
+int spi_nbyte_read(globals *g, int address, uint8_t *bytes, int len)
 {
 	const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
 		JEDEC_READ,
@@ -964,7 +964,7 @@ int spi_nbyte_read(int address, uint8_t *bytes, int len)
 	};
 
 	/* Send Read */
-	return spi_send_command(sizeof(cmd), len, cmd, bytes);
+	return spi_send_command(g, sizeof(cmd), len, cmd, bytes);
 }
 
 /*
@@ -972,7 +972,7 @@ int spi_nbyte_read(int address, uint8_t *bytes, int len)
  * FIXME: Use the chunk code from Michael Karcher instead.
  * Each page is read separately in chunks with a maximum size of chunksize.
  */
-int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
+int spi_read_chunked(globals *g, struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
 {
 	int rc = 0;
 	int i, j, starthere, lenhere;
@@ -996,7 +996,7 @@ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len,
 		lenhere = min(start + len, (i + 1) * page_size) - starthere;
 		for (j = 0; j < lenhere; j += chunksize) {
 			toread = min(chunksize, lenhere - j);
-			rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread);
+			rc = spi_nbyte_read(g, starthere + j, buf + starthere - start + j, toread);
 			if (rc)
 				break;
 		}
@@ -1012,7 +1012,7 @@ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len,
  * FIXME: Use the chunk code from Michael Karcher instead.
  * Each page is written separately in chunks with a maximum size of chunksize.
  */
-int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
+int spi_write_chunked(globals *g, struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
 {
 	int rc = 0;
 	int i, j, starthere, lenhere;
@@ -1041,11 +1041,11 @@ int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len,
 		lenhere = min(start + len, (i + 1) * page_size) - starthere;
 		for (j = 0; j < lenhere; j += chunksize) {
 			towrite = min(chunksize, lenhere - j);
-			rc = spi_nbyte_program(starthere + j, buf + starthere - start + j, towrite);
+			rc = spi_nbyte_program(g, starthere + j, buf + starthere - start + j, towrite);
 			if (rc)
 				break;
-			while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-				programmer_delay(10);
+			while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+				programmer_delay(g, 10);
 		}
 		if (rc)
 			break;
@@ -1061,22 +1061,22 @@ int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len,
  * (e.g. due to size constraints in IT87* for over 512 kB)
  */
 /* real chunksize is 1, logical chunksize is 1 */
-int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len)
+int spi_chip_write_1(globals *g, struct flashchip *flash, uint8_t *buf, int start, int len)
 {
 	int i, result = 0;
 
 	for (i = start; i < start + len; i++) {
-		result = spi_byte_program(i, buf[i - start]);
+		result = spi_byte_program(g, i, buf[i - start]);
 		if (result)
 			return 1;
-		while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-			programmer_delay(10);
+		while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+			programmer_delay(g, 10);
 	}
 
 	return 0;
 }
 
-int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len)
+int spi_aai_write(globals *g, struct flashchip *flash, uint8_t *buf, int start, int len)
 {
 	uint32_t pos = start;
 	int result;
@@ -1115,7 +1115,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len)
 	case SPI_CONTROLLER_WBSIO:
 		msg_perr("%s: impossible with this SPI controller,"
 				" degrading to byte program\n", __func__);
-		return spi_chip_write_1(flash, buf, start, len);
+		return spi_chip_write_1(g, flash, buf, start, len);
 #endif
 #endif
 	default:
@@ -1131,7 +1131,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len)
 	if (start % 2) {
 		msg_cerr("%s: start address not even! Please report a bug at "
 			 "flashrom@flashrom.org\n", __func__);
-		if (spi_chip_write_1(flash, buf, start, start % 2))
+		if (spi_chip_write_1(g, flash, buf, start, start % 2))
 			return SPI_GENERIC_ERROR;
 		pos += start % 2;
 		cmds[1].writearr = (const unsigned char[]){
@@ -1154,7 +1154,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len)
 	}
 
 
-	result = spi_send_multicommand(cmds);
+	result = spi_send_multicommand(g, cmds);
 	if (result) {
 		msg_cerr("%s failed during start command execution\n",
 			 __func__);
@@ -1163,8 +1163,8 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len)
 		 */
 		return result;
 	}
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-		programmer_delay(10);
+	while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+		programmer_delay(g, 10);
 
 	/* We already wrote 2 bytes in the multicommand step. */
 	pos += 2;
@@ -1173,19 +1173,19 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len)
 	while (pos < start + len - 1) {
 		cmd[1] = buf[pos++ - start];
 		cmd[2] = buf[pos++ - start];
-		spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL);
-		while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-			programmer_delay(10);
+		spi_send_command(g, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL);
+		while (spi_read_status_register(g) & JEDEC_RDSR_BIT_WIP)
+			programmer_delay(g, 10);
 	}
 
 	/* Use WRDI to exit AAI mode. This needs to be done before issuing any
 	 * other non-AAI command.
 	 */
-	spi_write_disable();
+	spi_write_disable(g);
 
 	/* Write remaining byte (if any). */
 	if (pos < start + len) {
-		if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2))
+		if (spi_chip_write_1(g, flash, buf + pos - start, pos, pos % 2))
 			return SPI_GENERIC_ERROR;
 		pos += pos % 2;
 	}
-- 
1.7.6

