flashrom v1.2 on Linux 5.10.0-8-amd64 (x86_64)

flashrom is free software, get the source code at https://flashrom.org

flashrom was built with libpci 3.6.4, GCC 9.2.1 20200224, little endian

Command line (7 args): flashrom --programmer internal -V -c MX25L3273E -r UEV.bin

Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).

Initializing internal programmer

/sys/class/mtd/mtd0 does not exist

No coreboot table found.

Using Internal DMI decoder.

No DMI table found.

Found chipset "Intel P55" with PCI ID 8086:3b02.

This chipset is marked as untested. If you are using an up-to-date version

of flashrom *and* were (not) able to successfully update your firmware with it,

then please email a report to flashrom@flashrom.org including a verbose (-V) log.

Thank you!

Enabling flash write... Root Complex Register Block address = 0xfed1c000

GCS = 0xc61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI)

Top Swap: not enabled

0x7fffffff/0x7fffffff FWH IDSEL: 0x0

0x7fffffff/0x7fffffff FWH IDSEL: 0x0

0x7fffffff/0x7fffffff FWH IDSEL: 0x1

0x7fffffff/0x7fffffff FWH IDSEL: 0x1

0x7fffffff/0x7fffffff FWH IDSEL: 0x2

0x7fffffff/0x7fffffff FWH IDSEL: 0x2

0x7fffffff/0x7fffffff FWH IDSEL: 0x3

0x7fffffff/0x7fffffff FWH IDSEL: 0x3

0x7fffffff/0x7fffffff FWH IDSEL: 0x4

0x7fffffff/0x7fffffff FWH IDSEL: 0x5

0x7fffffff/0x7fffffff FWH IDSEL: 0x6

0x7fffffff/0x7fffffff FWH IDSEL: 0x7

0x7fffffff/0x7fffffff FWH decode enabled

0x7fffffff/0x7fffffff FWH decode enabled

0x7fffffff/0x7fffffff FWH decode enabled

0x7fffffff/0x7fffffff FWH decode enabled

0x7fffffff/0x7fffffff FWH decode enabled

0x7fffffff/0x7fffffff FWH decode enabled

0x7fffffff/0x7fffffff FWH decode enabled

0x7fffffff/0x7fffffff FWH decode enabled

0x7fffffff/0x7fffffff FWH decode disabled

0x7fffffff/0x7fffffff FWH decode disabled

0x7fffffff/0x7fffffff FWH decode disabled

0x7fffffff/0x7fffffff FWH decode disabled

Maximum FWH chip size: 0x100000 bytes

SPI Read Configuration: prefetching disabled, caching enabled, 

BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled

SPIBAR = 0x00007f5fce36a000 + 0x3800

0x04: 0xe008 (HSFS)

HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1

SPI Configuration is locked down.

Reading OPCODES... done

0x06: 0x0004 (HSFC)

HSFC: FGO=0, FCYCLE=2, FDBC=0, SME=0

0x50: 0x0000ffff (FRAP)

BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff

0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write.

0x58: 0x03ff0021 FREG1: BIOS region (0x00021000-0x003fffff) is read-write.

0x5C: 0x00200001 FREG2: Management Engine region (0x00001000-0x00020fff) is read-write.

0x74: 0x82c10021 PR0: Warning: 0x00021000-0x002c1fff is read-only.

0x78: 0x9fff02e6 PR1: Warning: 0x002e6000-0x01ffffff is read-only.

At least some flash regions are write protected. For write operations,

you should use a flash layout and include only writable regions. See

manpage for more details.

0x90: 0x04 (SSFS)

SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0

0x91: 0xf97f20 (SSFC)

SSFC: SCGO=0, ACS=0, SPOP=0, COP=2, DBC=63, SME=0, SCF=1

0x94: 0x5006     (PREOP)

0x96: 0x0c6c     (OPTYPE)

0x98: 0x0103029f (OPMENU)

0x9c: 0x00002005 (OPMENU+4)

0xa0: 0x00000000 (BBAR)

0xc4: 0x00000000 (LVSCC)

LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0

0xc8: 0x00002011 (UVSCC)

UVSCC: BES=0x1, WG=0, WSR=0, WEWS=1, EO=0x20

0xd0: 0x00000000 (FPB)

OK.

The following protocols are supported: SPI.

Probing for Macronix MX25L3273E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016

Found Macronix flash chip "MX25L3273E" (4096 kB, SPI) mapped at physical address 0x00000000ffc00000.

Chip status register is 0x00.

Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set

Chip status register: Bit 6 is not set

Chip status register: Block Protect 3 (BP3) is not set

Chip status register: Block Protect 2 (BP2) is not set

Chip status register: Block Protect 1 (BP1) is not set

Chip status register: Block Protect 0 (BP0) is not set

Chip status register: Write Enable Latch (WEL) is not set

Chip status register: Write In Progress (WIP/BUSY) is not set

This chip may contain one-time programmable memory. flashrom cannot read

and may never be able to write it, hence it may not be able to completely

clone the contents of this chip (see man page for details).

Reading flash... done.

Restoring MMIO space at 0x7f5fce36d8a0

Restoring PCI config space for 00:1f:0 reg 0xdc