On Mon, Apr 2, 2012 at 1:01 AM, Niklas Söderlund <niklas.soderlund@ericsson.com> wrote:

Hi,

I'm interested in reading and writing to the status register in much the same way as the ChomiumOS flashrom do with it's --wp-* commands. But in a more generic way say:

--sr-read
--sr-write 0xAA

I'm thinking of this implementation:
- Porting ChomiumOS writeprotect.c to flashrom
- Implement a pure read/write of status register
- Change the --wp-* commands to use the status register read/write functions

Is this anything the flashrom community is interested in? I'd love to get feedback on this. My knowledge of flashroms structure is not as comprehensive yet so suggestions on implementation is appreciated.

The porting of the ChomiumOS flashrom --wp-* is not necessary for my goal but I though it might be the right path to go for flashrom, please correct me if I'm wrong.

I can see how this would be handy for people who really know what they're doing. OTOH, please be aware that status register layout, especially with regard to block protection, is rather inconsistent. If you have scripts that rely on a specific register layout it will likely break when you switch chips. It would help to know exactly what you're trying to accomplish so that we can tell if it's really necessary (or even a good idea) to operate on the raw status register content.

Be advised that some newer SPI chips also have a second status register. LPC chips have a status register (or at least some do... I'm looking at the SST49LF016 datasheet), but the information provided is quite a bit different from what's to be expected on SPI chips.

For the Chrome/Chromium OS branch, we were really only trying to make a script-able interface for write-protecting regions of 25-series SPI flash. So for example, a script could write-protect the bottom half the chip by doing something like: flashrom --wp-range 0 $(($(flashrom --chip-size)/2)) --wp-enable

More food for thought on the subject of write-protection: http://www.flashrom.org/pipermail/flashrom/2011-February/005795.html . One issue we found is that 25-series and 26-series SPI chips tend to have drastically different block protection capabilities. 25-series chips usually have uniform block protection, where by you block protect 1/Nth the size of the chip, while 26-series is much more flexible. Supporting all the different variations presenting them to the user in a sane manner takes some thought.