On Tue, 24 May 2016 12:49:51 +0530 Hatim Kanchwala email@example.com wrote:
The GSoC coding period has started and I have been working on my first sub-project, adding support for 2nd status register. Most supported chips that have multiple registers (around 80%) have opcode 0x35 for reading SR2 and, opcode 0x01 for writing SR2. I have developed 3 models and would like to have some feedback on them.
- Integrate read/write SR2 with existing functions
- Define a feature bit FEATURE_SR2
- spi_read_status_register(), defined in spi25_statusreg.c, additionally
reads second status register depending on FEATURE_SR2 bit for that flash
- Change return to uint16_t for spi_read_status_register()
- spi_write_status_register_flag(), defined in spi25_statusreg.c,
considers higher byte of status to write to SR2, depending on FEATURE_SR2 bit for that flash. MERITS -
- Fits in elegantly with existing implementation (IMO). Most code in
flashrom stores status reads/writes in int, which can easily accommodate the 16 bits
- Very little hassle when editing struct flashchip in flashchips.c
- RDSR will take more time - will read SR2 even if not needed
- Define separate functions to read/write SR2
- Define spi_read_status_register2() to read only SR2
- Define spi_write_status_register2_flag() and
spi_write_status_register2() to write to SR2. This will read SR1 first, then (SR2 << 8 | SR1) will be written using WRSR
- Flexibility (as compared to 1.)
- Need to write more lines (compared to 1.) when dealing with struct
- struct status_register_layout
The ChromiumOS fork defines a struct status_register_layout in writeprotect.c, which contains only BP and SRP bits' information. PROPOSAL - Do a similar flashrom-wide definition, which contains all status register bits' information.
- Very detailed representation of information
- Too much work when adding support for new chips
- Overhaul of existing infrastructure
IMHO, the first model is the best among these 3. I would like to know what you guys think about these, whether you have some new idea. Looking forward to your feedback. Thanks for your time.
thanks Hatim for this summary. It may make sense if David could sum up the rationales behind the chromiumos implementation. AFAIK much of that is driven by the desire to not touch flashchips.c to ease later upstreaming. A more detailed explanation might help Hatim.
What I miss from Hatim's proposals is how use cases affect the various implementations. The main question that needs to be addressed before implementing any kind of infrastructure like this is: what do we want to do with it once it is there.
Till now (vanilla) flashrom did only access the status registers for gathering (and printing) the status, especially the write protection bits, and for unlocking said bits. In the future we want to at least be able to set various protections additionally. What else do we need? Some bits are relevant to 4B addressing and Quad I/O too for example...