Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP51", enabling flash write... OK.
Found chip "SST SST49LF040B" (512 KB) at physical address 0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom@coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Programming page: 0000 at address: 0x000000000001 at address: 0x000100000002 at address: 0x000200000003 at address: 0x000300000004 at address: 0x000400000005 at address: 0x000500000006 at address: 0x000600000007 at address: 0x00070000