i think the spi chips are wired to both south bridge and super I/O.<br>carl:<br>   i do not think that SB700 has this mechanism, it must be the time circuit of this patent.<br>i find that before booting bios, there is several seconds delay after powering up.<br>
<br><div class="gmail_quote">On Fri, Jul 16, 2010 at 3:17 PM, Andriy Gapon <span dir="ltr">&lt;<a href="mailto:avg@icyb.net.ua">avg@icyb.net.ua</a>&gt;</span> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
on 15/07/2010 21:09 Carl-Daniel Hailfinger said the following:<br>
<div class="im">&gt;<br>
&gt; Did you know that SB700 (and later) has its own Dual BIOS mechanism? If<br>
&gt; there is interest, I can help with implementing support for that feature<br>
&gt; in flashrom.<br>
<br>
</div>Does that mechanism require that flash chips are wired to the south bridge<br>
(handled by its SPI controller)?  Or is it a more generic mechanism?<br>
<br>
--<br>
<font color="#888888">Andriy Gapon<br>
</font><div><div></div><div class="h5"><br>
--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br>
</div></div></blockquote></div><br><br clear="all"><br>-- <br>Wang Qing Pei <br>Phone: 86+13426369984<br>