No problem :3<br>Default jumper position (enabled):<br><blockquote style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex" class="gmail_quote">&gt;&gt; sudo flashrom -p internal -VV<br>[sudo] password for vladislavbyk: <br>

flashrom v0.9.6.1-r1564 on Linux 3.5.4-1-ARCH (i686)<br>flashrom is free software, get the source code at <a href="http://www.flashrom.org" target="_blank">http://www.flashrom.org</a><br><br>flashrom was built with libpci 3.1.10, GCC 4.7.1 20120721 (prerelease), little endian<br>

Command line (3 args): flashrom -p internal -VV<br>Calibrating delay loop... OS timer resolution is 1 usecs, 1355M loops per second, 10 myus = 10 us, 100 myus = 97 us, 1000 myus = 1126 us, 10000 myus = 9925 us, 4 myus = 4 us, OK.<br>

Initializing internal programmer<br>No coreboot table found.<br>DMI string system-manufacturer: &quot;To Be Filled By O.E.M.&quot;<br>DMI string system-product-name: &quot;To Be Filled By O.E.M.&quot;<br>DMI string system-version: &quot;To Be Filled By O.E.M.&quot;<br>

DMI string baseboard-manufacturer: &quot;Foxconn&quot;<br>DMI string baseboard-product-name: &quot;H55MX-S Series&quot;<br>DMI string baseboard-version: &quot;1.1&quot;<br>DMI string chassis-type: &quot;Desktop&quot;<br>
Found ITE Super I/O, ID 0x8720 on port 0x2e<br>
Found chipset &quot;Intel H55&quot; with PCI ID 8086:3b06. Enabling flash write... <br>0xfff80000/0xffb80000 FWH IDSEL: 0x0<br>0xfff00000/0xffb00000 FWH IDSEL: 0x0<br>0xffe80000/0xffa80000 FWH IDSEL: 0x1<br>0xffe00000/0xffa00000 FWH IDSEL: 0x1<br>

0xffd80000/0xff980000 FWH IDSEL: 0x2<br>0xffd00000/0xff900000 FWH IDSEL: 0x2<br>0xffc80000/0xff880000 FWH IDSEL: 0x3<br>0xffc00000/0xff800000 FWH IDSEL: 0x3<br>0xff700000/0xff300000 FWH IDSEL: 0x4<br>0xff600000/0xff200000 FWH IDSEL: 0x5<br>

0xff500000/0xff100000 FWH IDSEL: 0x6<br>0xff400000/0xff000000 FWH IDSEL: 0x7<br>0xfff80000/0xffb80000 FWH decode enabled<br>0xfff00000/0xffb00000 FWH decode enabled<br>0xffe80000/0xffa80000 FWH decode disabled<br>0xffe00000/0xffa00000 FWH decode disabled<br>

0xffd80000/0xff980000 FWH decode disabled<br>0xffd00000/0xff900000 FWH decode disabled<br>0xffc80000/0xff880000 FWH decode disabled<br>0xffc00000/0xff800000 FWH decode disabled<br>0xff700000/0xff300000 FWH decode disabled<br>

0xff600000/0xff200000 FWH decode disabled<br>0xff500000/0xff100000 FWH decode disabled<br>0xff400000/0xff000000 FWH decode disabled<br>Maximum FWH chip size: 0x100000 bytes<br>BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8<br>

Root Complex Register Block address = 0xfed1c000<br>GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI)<br>Top Swap : not enabled<br>SPIBAR = 0xfed1c000 + 0x3800<br>0x04: 0x6008 (HSFS)<br>HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0<br>

Programming OPCODES... <br>program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190<br>done<br>        OP        Type      Pre-OP<br>op[0]: 0x02, write w/  addr, none<br>op[1]: 0x03, read  w/  addr, none<br>op[2]: 0xd8, write w/  addr, none<br>

op[3]: 0x05, read  w/o addr, none<br>op[4]: 0x90, read  w/  addr, none<br>op[5]: 0x01, write w/o addr, none<br>op[6]: 0x9f, read  w/o addr, none<br>op[7]: 0xc7, write w/o addr, none<br>Pre-OP 0: 0x06, Pre-OP 1: 0x50<br>0x06: 0x0000 (HSFC)<br>

HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0<br>0x08: 0x00000000 (FADDR)<br>0x50: 0x00000a0b (FRAP)<br>BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b<br>0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br>

0x58: 0x07ff0700 FREG1: BIOS region (0x00700000-0x007fffff) is read-write.<br>0x5C: 0x06ff0001 FREG2: WARNING: Management Engine region (0x00001000-0x006fffff) is locked.<br>0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused.<br>

0x64: 0x00001fff FREG4: Platform Data region is unused.<br>0x74: 0x00000000 (PR0 is unused)<br>0x78: 0x00000000 (PR1 is unused)<br>0x7C: 0x00000000 (PR2 is unused)<br>0x80: 0x00000000 (PR3 is unused)<br>0x84: 0x00000000 (PR4 is unused)<br>

Please send a verbose log to <a href="mailto:flashrom@flashrom.org" target="_blank">flashrom@flashrom.org</a> if this board is not listed on<br><a href="http://flashrom.org/Supported_hardware#Supported_mainboards" target="_blank">http://flashrom.org/Supported_hardware#Supported_mainboards</a> yet.<br>

Writes have been disabled. You can enforce write support with the<br>ich_spi_force programmer option, but it will most likely harm your hardware!<br>If you force flashrom you will get no support if something breaks.<br>0x90: 0x00 (SSFS)<br>

SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0<br>0x91: 0xf84200 (SSFC)<br>SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0<br>0x94: 0x5006     (PREOP)<br>0x96: 0x463b     (OPTYPE)<br>0x98: 0x05d80302 (OPMENU)<br>0x9C: 0xc79f0190 (OPMENU+4)<br>

0xA0: 0x00000000 (BBAR)<br>0xC4: 0x00000000 (LVSCC)<br>LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0<br>0xC8: 0x00002001 (UVSCC)<br>UVSCC: BES=0x1, WG=0, WSR=0, WEWS=0, EO=0x20, VCL=0<br>0xD0: 0x00000000 (FPB)<br><br>

Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.<br>=== Content Section ===<br>FLVALSIG 0x0ff0a55a<br>FLMAP0   0x02040102<br>FLMAP1   0x10100206<br>FLMAP2   0x00000020<br><br>--- Details ---<br>NR          (Number of Regions):                     3<br>

FRBA        (Flash Region Base Address):         0x040<br>NC          (Number of Components):                  2<br>FCBA        (Flash Component Base Address):      0x020<br>ISL         (ICH/PCH Strap Length):                 16<br>

FISBA/FPSBA (Flash ICH/PCH Strap Base Address):  0x100<br>NM          (Number of Masters):                     3<br>FMBA        (Flash Master Base Address):         0x060<br>MSL/PSL     (MCH/PROC Strap Length):                 0<br>

FMSBA       (Flash MCH/PROC Strap Base Address): 0x200<br><br>=== Component Section ===<br>FLCOMP   0x0930001b<br>FLILL    0x00000000<br><br>--- Details ---<br>Component 1 density:             4 MB<br>Component 2 density:             4 MB<br>

Read Clock Frequency:           20 MHz<br>Read ID and Status Clock Freq.: 33 MHz<br>Write and Erase Clock Freq.:    33 MHz<br>Fast Read is supported.<br>Fast Read Clock Frequency:      33 MHz<br>No forbidden opcodes.<br>
<br>
=== Region Section ===<br>FLREG0   0x00000000<br>FLREG1   0x07ff0700<br>FLREG2   0x06ff0001<br>FLREG3   0x00001fff<br><br>--- Details ---<br>Region 0 (Descr.) 0x00000000 - 0x00000fff<br>Region 1 (BIOS  ) 0x00700000 - 0x007fffff<br>

Region 2 (ME    ) 0x00001000 - 0x006fffff<br>Region 3 (GbE   ) is unused.<br><br>=== Master Section ===<br>FLMSTR1  0x0a0b0000<br>FLMSTR2  0x0c0d0000<br>FLMSTR3  0x08080118<br><br>--- Details ---<br>      Descr. BIOS ME GbE Platf.<br>

BIOS    r     rw      rw     <br>ME      r         rw  rw     <br>GbE                   rw     <br><br>Enabling hardware sequencing due to multiple flash chips detected.<br>SPI Read Configuration: prefetching enabled, caching enabled, OK.<br>

No IT87* serial flash segment enabled.<br>The following protocols are supported: FWH, Programmer-specific.<br>Probing for Programmer Opaque flash chip, 0 kB: Found 2 attached SPI flash chips with a combined density of 8192 kB.<br>

There is only one partition containing the whole address space (0x000000 - 0x7fffff).<br>There are 2048 erase blocks with 4096 B each.<br>Found Programmer flash chip &quot;Opaque flash chip&quot; (8192 kB, Programmer-specific) at physical address 0x0.<br>

Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content<br>

Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>

Found Programmer flash chip &quot;Opaque flash chip&quot; (8192 kB, Programmer-specific).<br>No operations were specified.<br>Restoring MMIO space at 0xb77908a0<br>Restoring MMIO space at 0xb779089c<br>Restoring MMIO space at 0xb7790898<br>

Restoring MMIO space at 0xb7790896<br>Restoring MMIO space at 0xb7790894<br>Restoring PCI config space for 00:1f:0 reg 0xdc<br> &gt;&gt; <br></blockquote><br>Disabled:<br><blockquote style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex" class="gmail_quote">
^[[A%                                                                                                                                      &gt;&gt; sudo flashrom -p internal -VV<br>[sudo] password for vladislavbyk: <br>flashrom v0.9.6.1-r1564 on Linux 3.5.4-1-ARCH (i686)<br>
flashrom is free software, get the source code at <a href="http://www.flashrom.org">http://www.flashrom.org</a><br><br>flashrom was built with libpci 3.1.10, GCC 4.7.1 20120721 (prerelease), little endian<br>Command line (3 args): flashrom -p internal -VV<br>
Calibrating delay loop... OS timer resolution is 1 usecs, 1328M loops per second, 10 myus = 9 us, 100 myus = 96 us, 1000 myus = 1083 us, 10000 myus = 9907 us, 4 myus = 3 us, OK.<br>Initializing internal programmer<br>No coreboot table found.<br>
DMI string system-manufacturer: &quot;To Be Filled By O.E.M.&quot;<br>DMI string system-product-name: &quot;To Be Filled By O.E.M.&quot;<br>DMI string system-version: &quot;To Be Filled By O.E.M.&quot;<br>DMI string baseboard-manufacturer: &quot;Foxconn&quot;<br>
DMI string baseboard-product-name: &quot;H55MX-S Series&quot;<br>DMI string baseboard-version: &quot;1.1&quot;<br>DMI string chassis-type: &quot;Desktop&quot;<br>Found ITE Super I/O, ID 0x8720 on port 0x2e<br>Found chipset &quot;Intel H55&quot; with PCI ID 8086:3b06. Enabling flash write... <br>
0xfff80000/0xffb80000 FWH IDSEL: 0x0<br>0xfff00000/0xffb00000 FWH IDSEL: 0x0<br>0xffe80000/0xffa80000 FWH IDSEL: 0x1<br>0xffe00000/0xffa00000 FWH IDSEL: 0x1<br>0xffd80000/0xff980000 FWH IDSEL: 0x2<br>0xffd00000/0xff900000 FWH IDSEL: 0x2<br>
0xffc80000/0xff880000 FWH IDSEL: 0x3<br>0xffc00000/0xff800000 FWH IDSEL: 0x3<br>0xff700000/0xff300000 FWH IDSEL: 0x4<br>0xff600000/0xff200000 FWH IDSEL: 0x5<br>0xff500000/0xff100000 FWH IDSEL: 0x6<br>0xff400000/0xff000000 FWH IDSEL: 0x7<br>
0xfff80000/0xffb80000 FWH decode enabled<br>0xfff00000/0xffb00000 FWH decode enabled<br>0xffe80000/0xffa80000 FWH decode disabled<br>0xffe00000/0xffa00000 FWH decode disabled<br>0xffd80000/0xff980000 FWH decode disabled<br>
0xffd00000/0xff900000 FWH decode disabled<br>0xffc80000/0xff880000 FWH decode disabled<br>0xffc00000/0xff800000 FWH decode disabled<br>0xff700000/0xff300000 FWH decode disabled<br>0xff600000/0xff200000 FWH decode disabled<br>
0xff500000/0xff100000 FWH decode disabled<br>0xff400000/0xff000000 FWH decode disabled<br>Maximum FWH chip size: 0x100000 bytes<br>BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8<br>Root Complex Register Block address = 0xfed1c000<br>
GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI)<br>Top Swap : not enabled<br>SPIBAR = 0xfed1c000 + 0x3800<br>0x04: 0x4008 (HSFS)<br>HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=0, FDV=1, FLOCKDN=0<br>
The Flash Descriptor Security Override Strap-Pin is set. Restrictions implied<br>by the FRAP and FREG registers are NOT in effect. Please note that Protected<br>Range (PR) restrictions still apply.<br>Programming OPCODES... <br>
program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190<br>done<br>        OP        Type      Pre-OP<br>op[0]: 0x02, write w/  addr, none<br>op[1]: 0x03, read  w/  addr, none<br>op[2]: 0xd8, write w/  addr, none<br>
op[3]: 0x05, read  w/o addr, none<br>op[4]: 0x90, read  w/  addr, none<br>op[5]: 0x01, write w/o addr, none<br>op[6]: 0x9f, read  w/o addr, none<br>op[7]: 0xc7, write w/o addr, none<br>Pre-OP 0: 0x06, Pre-OP 1: 0x50<br>0x06: 0x0000 (HSFC)<br>
HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0<br>0x08: 0x00000000 (FADDR)<br>0x50: 0x0000ffff (FRAP)<br>BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff<br>0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write.<br>
0x58: 0x07ff0700 FREG1: BIOS region (0x00700000-0x007fffff) is read-write.<br>0x5C: 0x06ff0001 FREG2: Management Engine region (0x00001000-0x006fffff) is read-write.<br>0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused.<br>
0x64: 0x00001fff FREG4: Platform Data region is unused.<br>0x74: 0x00000000 (PR0 is unused)<br>0x78: 0x00000000 (PR1 is unused)<br>0x7C: 0x00000000 (PR2 is unused)<br>0x80: 0x00000000 (PR3 is unused)<br>0x84: 0x00000000 (PR4 is unused)<br>
0x90: 0x00 (SSFS)<br>SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0<br>0x91: 0xf84200 (SSFC)<br>SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0<br>0x94: 0x5006     (PREOP)<br>0x96: 0x463b     (OPTYPE)<br>0x98: 0x05d80302 (OPMENU)<br>
0x9C: 0xc79f0190 (OPMENU+4)<br>0xA0: 0x00000000 (BBAR)<br>0xC4: 0x00000000 (LVSCC)<br>LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0<br>0xC8: 0x00002001 (UVSCC)<br>UVSCC: BES=0x1, WG=0, WSR=0, WEWS=0, EO=0x20, VCL=0<br>
0xD0: 0x00000000 (FPB)<br><br>Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.<br>=== Content Section ===<br>FLVALSIG 0x0ff0a55a<br>FLMAP0   0x02040102<br>FLMAP1   0x10100206<br>FLMAP2   0x00000020<br>
<br>--- Details ---<br>NR          (Number of Regions):                     3<br>FRBA        (Flash Region Base Address):         0x040<br>NC          (Number of Components):                  2<br>FCBA        (Flash Component Base Address):      0x020<br>
ISL         (ICH/PCH Strap Length):                 16<br>FISBA/FPSBA (Flash ICH/PCH Strap Base Address):  0x100<br>NM          (Number of Masters):                     3<br>FMBA        (Flash Master Base Address):         0x060<br>
MSL/PSL     (MCH/PROC Strap Length):                 0<br>FMSBA       (Flash MCH/PROC Strap Base Address): 0x200<br><br>=== Component Section ===<br>FLCOMP   0x0930001b<br>FLILL    0x00000000<br><br>--- Details ---<br>Component 1 density:             4 MB<br>
Component 2 density:             4 MB<br>Read Clock Frequency:           20 MHz<br>Read ID and Status Clock Freq.: 33 MHz<br>Write and Erase Clock Freq.:    33 MHz<br>Fast Read is supported.<br>Fast Read Clock Frequency:      33 MHz<br>
No forbidden opcodes.<br><br>=== Region Section ===<br>FLREG0   0x00000000<br>FLREG1   0x07ff0700<br>FLREG2   0x06ff0001<br>FLREG3   0x00001fff<br><br>--- Details ---<br>Region 0 (Descr.) 0x00000000 - 0x00000fff<br>Region 1 (BIOS  ) 0x00700000 - 0x007fffff<br>
Region 2 (ME    ) 0x00001000 - 0x006fffff<br>Region 3 (GbE   ) is unused.<br><br>=== Master Section ===<br>FLMSTR1  0x0a0b0000<br>FLMSTR2  0x0c0d0000<br>FLMSTR3  0x08080118<br><br>--- Details ---<br>      Descr. BIOS ME GbE Platf.<br>
BIOS    r     rw      rw     <br>ME      r         rw  rw     <br>GbE                   rw     <br><br>Enabling hardware sequencing due to multiple flash chips detected.<br>SPI Read Configuration: prefetching enabled, caching enabled, OK.<br>
No IT87* serial flash segment enabled.<br>The following protocols are supported: FWH, Programmer-specific.<br>Probing for Programmer Opaque flash chip, 0 kB: Found 2 attached SPI flash chips with a combined density of 8192 kB.<br>
There is only one partition containing the whole address space (0x000000 - 0x7fffff).<br>There are 2048 erase blocks with 4096 B each.<br>Found Programmer flash chip &quot;Opaque flash chip&quot; (8192 kB, Programmer-specific) at physical address 0x0.<br>
Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content<br>
Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x4e, id2 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash content<br>
Found Programmer flash chip &quot;Opaque flash chip&quot; (8192 kB, Programmer-specific).<br>No operations were specified.<br>Restoring MMIO space at 0xb77438a0<br>Restoring MMIO space at 0xb774389c<br>Restoring MMIO space at 0xb7743898<br>
Restoring MMIO space at 0xb7743896<br>Restoring MMIO space at 0xb7743894<br>Restoring PCI config space for 00:1f:0 reg 0xdc<br></blockquote><br>Btw, maybe you have jabber or icq? :) <span id="result_box" class="short_text" lang="en"><span class="hps">It would be convenient)</span></span><div class="gmail_quote">
2012/10/2 Stefan Tauner <span dir="ltr">&lt;<a href="mailto:stefan.tauner@student.tuwien.ac.at" target="_blank">stefan.tauner@student.tuwien.ac.at</a>&gt;</span><br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div>On Tue, 2 Oct 2012 17:41:21 +0400<br>
Владислав Быков &lt;<a href="mailto:vladislavbyk1@gmail.com" target="_blank">vladislavbyk1@gmail.com</a>&gt; wrote:<br>
<br>
&gt; Yep, i toggle jumper, it&#39;s named MFG. It&#39;s should be disable (writed to<br>
&gt; mainboard manual) until i start flash.<br>
<br>
</div>Ok, thanks, can you please run &quot;flashrom -p internal -VV&quot; with the<br>
jumper in the previous/untoggled/default position and send us the<br>
output? I would like to know if/how the contents of the registers<br>
change by this exactly. This is not clearly documented publicly by<br>
Intel but might be helpful to us in the future.<br>
<div><div><br>
--<br>
Kind regards/Mit freundlichen Grüßen, Stefan Tauner<br>
</div></div></blockquote></div><br>