flashrom v0.9.4-r1395 on Linux 2.6.18.6-2g2g (i686), built with libpci 2.1.99-test8, GCC 4.0.2 20051125 (Red Hat 4.0.2-8), little endian
Calibrating delay loop... OK.
Found chipset "Intel ICH7M". Enabling flash write... OK.
This chipset supports the following protocols: FWH.
Found SST flash chip "SST49LF004A/B" (512 kB, FWH) at physical address 0xfff80000.
Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
Reading old flash chip contents... done.
Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x3f7
ERASE FAILED!
Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0xbea
ERASE FAILED!
FAILED!
Uh oh. Erase/write failed. Checking if anything changed.
Good. It seems nothing was changed.
Writing to the flash chip apparently didn't do anything.
This means we have to add special support for your board, programmer or flash chip.
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You may now reboot or simply leave the machine running.