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This is an external email, beware of phishing emails. Please pay close attention to whether the email contains sensitive information

If I understand your question correctly, `–wp-status` command should
give you the info:
Prints the flash’s current status register protection mode and write
protection range.

Probably you have looked at that already, but just in case all
available commands are in the man page, or also can be read here:
https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fflashrom.org%2Fclassic_cli_manpage.html&data=05%7C02%7Cvlim%40gigadevice.com%7C4a985ef0e8814afd275908dc57cbf30f%7Cf84ba339959c4ab19b671e43414f945e%7C0%7C0%7C638481780720654286%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=loxAQPEWneQgWDlahCT1XZta0HrzfVPtM5GXkiT0qtQ%3D&reserved=0


On Sun, Apr 7, 2024 at 7:55 AM Vlim <vlim@gigadevice.com> wrote:
>
> Looked at it further and understood that it is determined by the BPx bits, tb bit.
> Is there a way I can read the status registers to make sure that all these bits match with the datasheet?
>
> Regards,
>
> Victor
>
>
> ________________________________
> From: Vlim <vlim@gigadevice.com>
> Sent: Friday, April 5, 2024 20:37
> To: Nikolai Artemiev <nartemiev@google.com>; Anastasia Klimchuk <aklm@chromium.org>
> Cc: flashrom@flashrom.org <flashrom@flashrom.org>; Peter Marheine <pmarheine@chromium.org>
> Subject: Re: [flashrom] Re: adding part #
>
> Thanks.
>
> How are the protection ranges defined?
> My device has ½ to 1/512.
> So I am missing 1/128, 1/256, 1/512.
> And I am getting some extra from 1/1024 to 1/8192.
>
> Please advise.
>
> Regards,
>
> Victor
>
>
>
> ________________________________
> From: Nikolai Artemiev <nartemiev@google.com>
> Sent: Tuesday, March 26, 2024 18:54
> To: Anastasia Klimchuk <aklm@chromium.org>
> Cc: Vlim <vlim@gigadevice.com>; flashrom@flashrom.org <flashrom@flashrom.org>; Peter Marheine <pmarheine@chromium.org>
> Subject: Re: [flashrom] Re: adding part #
>
> You don't often get email from nartemiev@google.com. Learn why this is important
> 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息
> This is an external email, beware of phishing emails. Please pay close attention to whether the email contains sensitive information
> Hi Victor,
>
> One thing to note with the printlock and unlock functions you mentioned earlier, i.e.:
>
> .printlock  = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
> .unlock     = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,
>
> These functions basically just allow flashrom to remove memory protection before writing to the chip. They can (and should) be omitted if you define reg_bits and decode_range in the chip entry, because that will enable full writeprotect support for the chip.
>
> The reason we still have unlock and printlock functions is for older chips that don't have reg_bits and decode_range defined.
>
> Cheers,
> Nik
>
>
>
> On Tue, Mar 26, 2024 at 4:32 PM Anastasia Klimchuk <aklm@chromium.org> wrote:
>
> I will try to answer to everything in one message, but feel free to
> ask more questions
>
> > Can you point me to the file that defines the commands?
>
> Most of them will be in include/spi.h
>
> It is a longer way if you want to trace implementation from, for
> example SPI_CHIP_READ, to the place where command is sent, but in case
> you would need it:
>
> you would need to go through the sequence of function calls, starting
> from `spi_chip_read` in spi.c and then look into the programmer code
> (for whichever is the programmer you are using) and see how that
> programmer implements spi read and send commands. Specifically look
> for `static const struct spi_master` in the programmer source code
> file.
>
> Default functions are in spi.c and spi25.c files.
>
> > How is Dual IO and Quad IO supported here?
>
> Currently not implemented, however it would be really great to
> implement it in the future (contributions are very welcome).
> We do have those aspirational comments in flashchips.c , for example
> (I am just copying from some chip)
>
> .write = SPI_CHIP_WRITE256, /* Dual I/O  (0xA2) supported */
> .read = SPI_CHIP_READ, /* Fast read (0x0B), dual I/O  (0x3B) supported */
>
> So maybe you can add similar comments for the chip definition for now.
>
> On Tue, Mar 26, 2024 at 5:27 AM Vlim <vlim@gigadevice.com> wrote:
> >
> > Hi,
> >
> > Can you point me to the file that defines the commands?
> > Like SPI_CHIP_READ being 0x0b.
> >
> > Thanks,
> >
> > Victor
> >
> > ________________________________
> > From: Anastasia Klimchuk <aklm@chromium.org>
> > Sent: Thursday, March 21, 2024 23:32
> > To: Vlim <vlim@gigadevice.com>; flashrom@flashrom.org <flashrom@flashrom.org>
> > Cc: Peter Marheine <pmarheine@chromium.org>
> > Subject: Re: [flashrom] Re: adding part #
> >
> > [You don't often get email from aklm@chromium.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息
> > This is an external email, beware of phishing emails. Please pay close attention to whether the email contains sensitive information
> >
> > For these two (printlock and unlock), you need to pick the function
> > which handles the highest BP bit that chip supports. In your example,
> > if a chip supports bits BP0-BP4 the correct functions are those with
> > BP4 in the name. So you did it all right.
> >
> > If the chip supports write protection, you also need to set .reg_bits
> > in chip definition. For this you need to have a look at struct
> > reg_bit_map in include/flash.h, it has comments on what each bit in
> > the struct means.
> >
> >
> > On Fri, Mar 22, 2024 at 7:22 AM Vlim <vlim@gigadevice.com> wrote:
> > >
> > > Thanks, Anastasia,
> > >
> > > Can you please explain this statement,
> > >
> > > .printlock  = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
> > > .unlock     = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,
> > >
> > > Looks like this is to support memory array protection. But it needs BP0-BP4.
> > > Do I need to specify BP0 to BP3 as well?
> > > Or I specify the setting when I initiate the flashrom programming command?
> > >
> > > Regards,
> > >
> > > Victor
> > >
> > > ________________________________
> > > From: Anastasia Klimchuk <aklm@chromium.org>
> > > Sent: Thursday, March 21, 2024 05:32
> > > To: Vlim <vlim@gigadevice.com>; flashrom@flashrom.org <flashrom@flashrom.org>
> > > Cc: Peter Marheine <pmarheine@chromium.org>
> > > Subject: [flashrom] Re: adding part #
> > >
> > > You don't often get email from aklm@chromium.org. Learn why this is important
> > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息
> > > This is an external email, beware of phishing emails. Please pay close attention to whether the email contains sensitive information
> > > Hello Victor,
> > >
> > > Various feature bits are defined as macros in include/flash.h , some of them have comments explaining what they do. If the feature name is not descriptive, and there is no comment, but you think you might need this feature: feel free to ask. I would try to add comments later.
> > >
> > > SPI_DISABLE_BLOCKPROTECT_BP4_SRWD and other unlock functions as in spi25_statusreg.c. Those functions have comments, hopefully this can help!
> > >
> > > On Thu, Mar 21, 2024 at 2:48 PM Vlim <vlim@gigadevice.com> wrote:
> > >
> > > Thanks, Peter,
> > >
> > > Where can I find the definition of terms like,
> > >
> > > .feature_bits     = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2,
> > > SPI_DISABLE_BLOCKPROTECT_BP4_SRWD
> > >
> > > Regards,
> > >
> > > Victor
> > >
> > >
> > > ________________________________
> > > From: Peter Marheine <pmarheine@chromium.org>
> > > Sent: Tuesday, March 19, 2024 15:42
> > > To: Vlim <vlim@gigadevice.com>
> > > Cc: flashrom@flashrom.org <flashrom@flashrom.org>
> > > Subject: Re: [flashrom] adding part #
> > >
> > > You don't often get email from pmarheine@chromium.org. Learn why this is important
> > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息
> > > This is an external email, beware of phishing emails. Please pay close attention to whether the email contains sensitive information
> > > Our "how to add a new chip" documentation should point you in the right direction: https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fflashrom.org%2Fcontrib_howtos%2Fhow_to_add_new_chip.html&data=05%7C02%7Cvlim%40gigadevice.com%7C4a985ef0e8814afd275908dc57cbf30f%7Cf84ba339959c4ab19b671e43414f945e%7C0%7C0%7C638481780720666315%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=cjfc4ZWjqKXvQ6frTNbaehlcuZx4AcREFMBgP8I5FDE%3D&reserved=0
> > >
> > > But feel free to ask further questions if anything there doesn't seem sufficient for your needs.
> > >
> > > On Wed, Mar 20, 2024 at 6:31 AM Vlim <vlim@gigadevice.com> wrote:
> > >
> > > Hi, FlashRom team,
> > >
> > > I am the FAE director in Gigadevice and I would like to add some part #s to the flashchip.c and flashchip.h.
> > > Can you please provide some guidance?
> > >
> > > Regards,
> > >
> > > Victor Lim
> > > FAE Director
> > > GigaDevice Semiconductor
> > > 4088833856
> > >
> > > _______________________________________________
> > > flashrom mailing list -- flashrom@flashrom.org
> > > To unsubscribe send an email to flashrom-leave@flashrom.org
> > >
> > > _______________________________________________
> > > flashrom mailing list -- flashrom@flashrom.org
> > > To unsubscribe send an email to flashrom-leave@flashrom.org
> > >
> > >
> > >
> > > --
> > > Anastasia.
> >
> >
> >
> > --
> > Anastasia.
>
>
>
> --
> Anastasia.
> _______________________________________________
> flashrom mailing list -- flashrom@flashrom.org
> To unsubscribe send an email to flashrom-leave@flashrom.org



--
Anastasia.