root@test-adrian1:..src/flashrom> ./flashrom -r old.rom flashrom v0.9.1-r767 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "ST M50FW040" (512 KB, FWH) at physical address 0xfff80000. Reading flash... done. root@test-adrian1:..src/flashrom> ./flashrom -w old.rom flashrom v0.9.1-r767 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "ST M50FW040" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED 0007 at address: 0x00070000SKIPPED COMPLETE. Verifying flash... VERIFIED. root@test-adrian1:..src/flashrom> ./flashrom -w 8ipekpt2.f10 flashrom v0.9.1-r767 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "ST M50FW040" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: 0000 at address: 0x00000000ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0x1549 ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom@flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! root@test-adrian1:..src/flashrom>