[flashrom] [PATCH] drkaiser, gfxnvidia: MEM BAR fixes

[Carl-Daniel Hailfinger]

Hi Joerg, hi Uwe,

could you two please test this patch against latest flashrom on your
hardware (Dr. Kaiser FPGA, Nvidia graphics card)?

Use the BAR value returned by pcidev_init which automatically applies
the correct BAR mask for the drkaiser driver.
Truncate flash chip addresses to fit into the 128 kB memory window for
drkaiser and pick the same window size for gfxnvidia.

Uwe: I'm not sure if 128kB are an appropriate size for gfxnvidia.
Looking at the size of the mapping, 8 MB are probably possible, but I
have no idea if that mapping is any indicator of possible chip size or
just a leftover artifact.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-drkaiser_pcibar_mask_mem_bounds_checking/drkaiser.c
===================================================================
--- flashrom-drkaiser_pcibar_mask_mem_bounds_checking/drkaiser.c	(Revision 997)
+++ flashrom-drkaiser_pcibar_mask_mem_bounds_checking/drkaiser.c	(Arbeitskopie)
@@ -28,6 +28,9 @@
 #define PCI_MAGIC_DRKAISER_ADDR		0x50
 #define PCI_MAGIC_DRKAISER_VALUE	0xa971

+/* Mask to restrict flash accesses to the 128kB memory window. */
+#define DRKAISER_MEMMAP_MASK		((1 << 17) - 1)
+
 struct pcidev_status drkaiser_pcidev[] = {
    {0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"},
    {},
@@ -40,16 +43,13 @@
    uint32_t addr;

get_io_perms();
-	pcidev_init(PCI_VENDOR_ID_DRKAISER, PCI_BASE_ADDRESS_2,
-		    drkaiser_pcidev, programmer_param);
+	addr = pcidev_init(PCI_VENDOR_ID_DRKAISER, PCI_BASE_ADDRESS_2,
+			   drkaiser_pcidev, programmer_param);

/* Write magic register to enable flash write. */
    pci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR,
    	       PCI_MAGIC_DRKAISER_VALUE);

-	/* TODO: Mask lower bits? How many? 3? 7? */
-	addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) & ~0x03;
-
    /* Map 128KB flash memory window. */
    drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory",
    		       addr, 128 * 1024);
@@ -70,10 +70,10 @@

void drkaiser_chip_writeb(uint8_t val, chipaddr addr)
 {
-	mmio_writeb(val, drkaiser_bar + addr);
+	mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK));
 }

uint8_t drkaiser_chip_readb(const chipaddr addr)
 {
-	return mmio_readb(drkaiser_bar + addr);
+	return mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK));
 }
Index: flashrom-drkaiser_pcibar_mask_mem_bounds_checking/gfxnvidia.c
===================================================================
--- flashrom-drkaiser_pcibar_mask_mem_bounds_checking/gfxnvidia.c	(Revision 997)
+++ flashrom-drkaiser_pcibar_mask_mem_bounds_checking/gfxnvidia.c	(Arbeitskopie)
@@ -25,6 +25,11 @@

#define PCI_VENDOR_ID_NVIDIA	0x10de

+/* Mask to restrict flash accesses to a 128kB memory window.
+ * FIXME: Is this size a one-fits-all or card dependent?
+ */
+#define GFXNVIDIA_MEMMAP_MASK		((1 << 17) - 1)
+
 uint8_t *nvidia_bar;

struct pcidev_status gfx_nvidia[] = {
@@ -95,10 +100,10 @@

void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr)
 {
-	mmio_writeb(val, nvidia_bar + addr);
+	mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
 }

uint8_t gfxnvidia_chip_readb(const chipaddr addr)
 {
-	return mmio_readb(nvidia_bar + addr);
+	return mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
 }