For completeness, the proposed change is at https://review.coreboot.org/c/flashrom/+/81545

I've tested it myself (and added a unit test) and am fairly confident everything works well, but if anybody has a "weirder" machine than an x86 PC to test on, additional coverage would be helpful.

On Fri, Apr 5, 2024 at 11:13 PM Anastasia Klimchuk <aklm@chromium.org> wrote:

> do you want to keep around such legacy code
> (increasing the maintenance load) in the codebase forever?

No I don't want to keep such code forever to maintain, mainly because
it won't be needed forever.
But dropping support for DOS will be a separate effort (with dedicated
threads and announcements). I don't think it should be like "while we
are here, let's also drop DOS", it's a bigger effort than "while we
are here".

> For example, some chips use the toggle bit detection to check for a
> finished write.

Do you know, are such chips marked in flashchips definition, how do we
know which ones are like this?
I understand from your words this is a subset of older non-SPI
(LPC/FWH/parallel) flash chips but which ones?

Also relevant to delays: are those the same chips that need extra delay 1s?
For context, comments here https://review.coreboot.org/c/flashrom/+/80807
Do you maybe remember how to find them in flashchips?

As I understand, there are some small(?) number of older(?) chips
which need special treatment on delays, it would be so helpful to find
out which ones exactly.

> Focusing on the 99% might yield enormous
> cleanup opportunities.

Yes, that's a really good observation.
I have such thoughts in the background.

--
Anastasia.

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