diff --git a/Makefile b/Makefile index d5132a7..9245624 100644 --- a/Makefile +++ b/Makefile @@ -33,27 +33,27 @@ ifneq ($(OS_ARCH), SunOS) STRIP_ARGS = -s endif ifeq ($(OS_ARCH), Darwin) CPPFLAGS += -I/opt/local/include -I/usr/local/include LDFLAGS += -framework IOKit -framework DirectIO -L/opt/local/lib -L/usr/local/lib endif ifeq ($(OS_ARCH), FreeBSD) CPPFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib endif CHIP_OBJS = jedec.o stm50flw0x0x.o w39v040c.o w39v080fa.o sharplhf00l04.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o LIB_OBJS = layout.o CLI_OBJS = flashrom.o cli_classic.o cli_output.o print.o PROGRAMMER_OBJS = udelay.o programmer.o all: pciutils features dep $(PROGRAM) # Set the flashrom version string from the highest revision number # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. diff --git a/board_enable.c b/board_enable.c index 4278b6d..71706c7 100644 --- a/board_enable.c +++ b/board_enable.c @@ -17,26 +17,27 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* * Contains the board specific flash enables. */ #include #include #include "flash.h" +#include "hwaccess.h" /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ /* Enter extended functions */ void w836xx_ext_enter(uint16_t port) { OUTB(0x87, port); OUTB(0x87, port); } /* Leave extended functions */ void w836xx_ext_leave(uint16_t port) diff --git a/buspirate_spi.c b/buspirate_spi.c index ecdd689..f1a0be1 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -13,26 +13,27 @@ * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include "flash.h" +#include "chipdrivers.h" #include "spi.h" /* Change this to #define if you want to test without a serial implementation */ #undef FAKE_COMMUNICATION #ifndef FAKE_COMMUNICATION int buspirate_serialport_setup(char *dev) { /* 115200bps, 8 databits, no parity, 1 stopbit */ sp_fd = sp_openserport(dev, 115200); return 0; } #else diff --git a/chipdrivers.h b/chipdrivers.h index 059100e..77d6bf2 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -7,35 +7,36 @@ * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * * - * Header file for flash chip drivers. Included from flash.h. + * Header file for flash chip drivers. * As a general rule, every function listed here should take a pointer to * struct flashchip as first parameter. */ #ifndef __CHIPDRIVERS_H__ #define __CHIPDRIVERS_H__ 1 /* spi.c, should probably be in spi_chip.c */ +int probe_spi_rdid_generic(struct flashchip *flash, int bytes); int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); int probe_spi_rems(struct flashchip *flash); int probe_spi_res(struct flashchip *flash); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); int spi_chip_erase_60_c7(struct flashchip *flash); int spi_chip_erase_d8(struct flashchip *flash); int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); diff --git a/chipset_enable.c b/chipset_enable.c index 1830eb2..f518db9 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -23,26 +23,27 @@ /* * Contains the chipset specific flash enables. */ #define _LARGEFILE64_SOURCE #include #include #include #include #include #include "flash.h" +#include "hwaccess.h" extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; /* * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and * 0xFFFE0000-0xFFFFFFFF ROM select enable. */ tmp = pci_read_byte(dev, 0x47); tmp |= 0x46; diff --git a/flash.h b/flash.h index ff2004c..d1a59b0 100644 --- a/flash.h +++ b/flash.h @@ -17,32 +17,34 @@ * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef __FLASH_H__ #define __FLASH_H__ 1 #include #include #include -#include "hwaccess.h" #ifdef _WIN32 #include #undef min #undef max #endif +#if NEED_PCI == 1 +#include +#endif typedef unsigned long chipaddr; enum programmer { #if INTERNAL_SUPPORT == 1 PROGRAMMER_INTERNAL, #endif #if DUMMY_SUPPORT == 1 PROGRAMMER_DUMMY, #endif #if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM, #endif @@ -671,16 +673,14 @@ void serprog_delay(int delay); typedef HANDLE fdtype; #else typedef int fdtype; #endif void sp_flush_incoming(void); fdtype sp_openserport(char *dev, unsigned int baud); void __attribute__((noreturn)) sp_die(char *msg); extern fdtype sp_fd; int serialport_shutdown(void); int serialport_write(unsigned char *buf, unsigned int writecnt); int serialport_read(unsigned char *buf, unsigned int readcnt); -#include "chipdrivers.h" - #endif /* !__FLASH_H__ */ diff --git a/flashchips.c b/flashchips.c index 875d5b3..45e67c6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14,26 +14,27 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "flash.h" #include "flashchips.h" +#include "chipdrivers.h" /** * List of supported flash chips. * * Please keep the list sorted by vendor name and chip name, so that * the output of 'flashrom -L' is alphabetically sorted. */ struct flashchip flashchips[] = { /* * .vendor = Vendor name * .name = Chip name * .bustype = Supported flash bus types (Parallel, LPC...) diff --git a/hwaccess.c b/hwaccess.c index 7f7b805..b637098 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -15,26 +15,27 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "flash.h" +#include "hwaccess.h" #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif void get_io_perms(void) { #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif defined(__FreeBSD__) || defined (__DragonFly__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { #else if (iopl(3) != 0) { diff --git a/hwaccess.h b/hwaccess.h index 89469b0..5fe0dd9 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -7,27 +7,27 @@ * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * * - * Header file for hardware access and OS abstraction. Included from flash.h. + * Header file for hardware access and OS abstraction. */ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 #if defined(__GLIBC__) #include #endif #if NEED_PCI == 1 #include #endif /* for iopl and outb under Solaris */ diff --git a/ichspi.c b/ichspi.c index 77d236a..9ab61ff 100644 --- a/ichspi.c +++ b/ichspi.c @@ -25,26 +25,27 @@ /* * This module is designed for supporting the devices * ST M25P40 * ST M25P80 * ST M25P16 * ST M25P32 already tested * ST M25P64 * AT 25DF321 already tested * */ #include #include "flash.h" +#include "chipdrivers.h" #include "spi.h" /* Change this to #define if you want lowlevel debugging of commands * sent to the ICH/VIA SPI controller. */ #undef COMM_DEBUG #ifdef COMM_DEBUG #define msg_comm_debug printf_debug #else #define msg_comm_debug(...) do {} while (0) #endif diff --git a/it87spi.c b/it87spi.c index fcbf086..be39872 100644 --- a/it87spi.c +++ b/it87spi.c @@ -16,26 +16,28 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* * Contains the ITE IT87* SPI specific routines */ #include #include #include "flash.h" +#include "hwaccess.h" +#include "chipdrivers.h" #include "spi.h" #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ int fast_spi = 1; /* Helper functions for most recent ITE IT87xx Super I/O chips */ #define CHIP_ID_BYTE1_REG 0x20 #define CHIP_ID_BYTE2_REG 0x21 void enter_conf_mode_ite(uint16_t port) diff --git a/jedec.c b/jedec.c index 055e910..fee7302 100644 --- a/jedec.c +++ b/jedec.c @@ -13,26 +13,27 @@ * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "flash.h" +#include "chipdrivers.h" #define MAX_REFLASH_TRIES 0x10 #define MASK_FULL 0xffff #define MASK_2AA 0x7ff #define MASK_AAA 0xfff /* Check one byte for odd parity */ uint8_t oddparity(uint8_t val) { val = (val ^ (val >> 4)) & 0xf; val = (val ^ (val >> 2)) & 0x3; return (val ^ (val >> 1)) & 0x1; } diff --git a/m29f400bt.c b/m29f400bt.c index e77572a..c394074 100644 --- a/m29f400bt.c +++ b/m29f400bt.c @@ -9,26 +9,27 @@ * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "flash.h" +#include "chipdrivers.h" /* WARNING! This chip uses the standard JEDEC Addresses in 16-bit mode as word addresses. In byte mode, 0xAAA has to be used instead of 0x555 and 0x555 instead of 0x2AA. Do *not* blindly replace with standard JEDEC functions. */ void write_page_m29f400bt(chipaddr bios, uint8_t *src, chipaddr dst, int page_size) { int i; for (i = 0; i < page_size; i++) { diff --git a/nic3com.c b/nic3com.c index d3dcce5..e3173ca 100644 --- a/nic3com.c +++ b/nic3com.c @@ -12,26 +12,27 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "flash.h" +#include "hwaccess.h" #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e #define INTERNAL_CONFIG 0x00 #define SELECT_REG_WINDOW 0x800 #define PCI_VENDOR_ID_3COM 0x10b7 uint32_t internal_conf; uint16_t id; struct pcidev_status nics_3com[] = { diff --git a/physmap.c b/physmap.c index fba7a53..7fec325 100644 --- a/physmap.c +++ b/physmap.c @@ -16,26 +16,27 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "flash.h" +#include "hwaccess.h" #ifdef __DARWIN__ #include #define MEM_DEV "DirectIO" void *sys_physmap(unsigned long phys_addr, size_t len) { return map_physical(phys_addr, len); } /* The OS X driver does not differentiate between mapping types. */ #define sys_physmap_rw_uncached sys_physmap diff --git a/pm49fl00x.c b/pm49fl00x.c index e8c498d..17a49f0 100644 --- a/pm49fl00x.c +++ b/pm49fl00x.c @@ -11,26 +11,27 @@ * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "flash.h" +#include "chipdrivers.h" void write_lockbits_49fl00x(chipaddr bios, int size, unsigned char bits, int block_size) { int i, left = size; for (i = 0; left >= block_size; i++, left -= block_size) { /* pm49fl002 */ if (block_size == 16384 && i % 2) continue; chip_writeb(bits, bios + (i * block_size) + 2); } diff --git a/sb600spi.c b/sb600spi.c index 9172eac..0cf797c 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -12,26 +12,27 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "flash.h" +#include "chipdrivers.h" #include "spi.h" /* This struct is unused, but helps visualize the SB600 SPI BAR layout. *struct sb600_spi_controller { * unsigned int spi_cntrl0; / * 00h * / * unsigned int restrictedcmd1; / * 04h * / * unsigned int restrictedcmd2; / * 08h * / * unsigned int spi_cntrl1; / * 0ch * / * unsigned int spi_cmdvalue0; / * 10h * / * unsigned int spi_cmdvalue1; / * 14h * / * unsigned int spi_cmdvalue2; / * 18h * / * unsigned int spi_fakeid; / * 1Ch * / *}; diff --git a/sharplhf00l04.c b/sharplhf00l04.c index 9669e20..d5ab38c 100644 --- a/sharplhf00l04.c +++ b/sharplhf00l04.c @@ -10,26 +10,27 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "flash.h" +#include "chipdrivers.h" // I need that Berkeley bit-map printer void print_lhf00l04_status(uint8_t status) { printf("%s", status & 0x80 ? "Ready:" : "Busy:"); printf("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:"); printf("%s", status & 0x20 ? "BE ERROR:" : "BE OK:"); printf("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:"); printf("%s", status & 0x8 ? "VP ERR:" : "VPP OK:"); printf("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:"); printf("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:"); } diff --git a/spi.c b/spi.c index 66f1db8..d9888bd 100644 --- a/spi.c +++ b/spi.c @@ -15,27 +15,27 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* * Contains the generic SPI framework */ #include #include "flash.h" #include "flashchips.h" -#include "spi.h" +#include "chipdrivers.h" enum spi_controller spi_controller = SPI_CONTROLLER_NONE; void *spibar = NULL; void spi_prettyprint_status_register(struct flashchip *flash); const struct spi_programmer spi_programmer[] = { { /* SPI_CONTROLLER_NONE */ .command = NULL, .multicommand = NULL, .read = NULL, .write_256 = NULL, }, @@ -139,191 +139,26 @@ int spi_send_command(unsigned int writecnt, unsigned int readcnt, } int spi_send_multicommand(struct spi_command *cmds) { if (!spi_programmer[spi_controller].multicommand) { fprintf(stderr, "%s called, but SPI is unsupported on this " "hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].multicommand(cmds); } -int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr) -{ - struct spi_command cmd[] = { - { - .writecnt = writecnt, - .readcnt = readcnt, - .writearr = writearr, - .readarr = readarr, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - return spi_send_multicommand(cmd); -} - -int default_spi_send_multicommand(struct spi_command *cmds) -{ - int result = 0; - for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { - result = spi_send_command(cmds->writecnt, cmds->readcnt, - cmds->writearr, cmds->readarr); - } - return result; -} - -static int spi_rdid(unsigned char *readarr, int bytes) -{ - const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; - int ret; - int i; - - ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); - if (ret) - return ret; - printf_debug("RDID returned"); - for (i = 0; i < bytes; i++) - printf_debug(" 0x%02x", readarr[i]); - printf_debug(". "); - return 0; -} - -static int spi_rems(unsigned char *readarr) -{ - unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; - uint32_t readaddr; - int ret; - - ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); - if (ret == SPI_INVALID_ADDRESS) { - /* Find the lowest even address allowed for reads. */ - readaddr = (spi_get_valid_read_addr() + 1) & ~1; - cmd[1] = (readaddr >> 16) & 0xff, - cmd[2] = (readaddr >> 8) & 0xff, - cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); - } - if (ret) - return ret; - printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]); - return 0; -} - -static int spi_res(unsigned char *readarr) -{ - unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; - uint32_t readaddr; - int ret; - - ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); - if (ret == SPI_INVALID_ADDRESS) { - /* Find the lowest even address allowed for reads. */ - readaddr = (spi_get_valid_read_addr() + 1) & ~1; - cmd[1] = (readaddr >> 16) & 0xff, - cmd[2] = (readaddr >> 8) & 0xff, - cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); - } - if (ret) - return ret; - printf_debug("RES returned %02x. ", readarr[0]); - return 0; -} - -int spi_write_enable(void) -{ - const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; - int result; - - /* Send WREN (Write Enable) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); - - if (result) - fprintf(stderr, "%s failed\n", __func__); - - return result; -} - -int spi_write_disable(void) -{ - const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; - - /* Send WRDI (Write Disable) */ - return spi_send_command(sizeof(cmd), 0, cmd, NULL); -} - -static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) -{ - unsigned char readarr[4]; - uint32_t id1; - uint32_t id2; - - if (spi_rdid(readarr, bytes)) - return 0; - - if (!oddparity(readarr[0])) - printf_debug("RDID byte 0 parity violation. "); - - /* Check if this is a continuation vendor ID */ - if (readarr[0] == 0x7f) { - if (!oddparity(readarr[1])) - printf_debug("RDID byte 1 parity violation. "); - id1 = (readarr[0] << 8) | readarr[1]; - id2 = readarr[2]; - if (bytes > 3) { - id2 <<= 8; - id2 |= readarr[3]; - } - } else { - id1 = readarr[0]; - id2 = (readarr[1] << 8) | readarr[2]; - } - - printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); - - if (id1 == flash->manufacture_id && id2 == flash->model_id) { - /* Print the status register to tell the - * user about possible write protection. - */ - spi_prettyprint_status_register(flash); - - return 1; - } - - /* Test if this is a pure vendor match. */ - if (id1 == flash->manufacture_id && - GENERIC_DEVICE_ID == flash->model_id) - return 1; - - /* Test if there is any vendor ID. */ - if (GENERIC_MANUF_ID == flash->manufacture_id && - id1 != 0xff) - return 1; - - return 0; -} - -int probe_spi_rdid(struct flashchip *flash) -{ - return probe_spi_rdid_generic(flash, 3); -} - /* support 4 bytes flash ID */ int probe_spi_rdid4(struct flashchip *flash) { /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif #if FT2232_SPI_SUPPORT == 1 @@ -336,811 +171,46 @@ int probe_spi_rdid4(struct flashchip *flash) case SPI_CONTROLLER_BUSPIRATE: #endif #if DEDIPROG_SUPPORT == 1 case SPI_CONTROLLER_DEDIPROG: #endif return probe_spi_rdid_generic(flash, 4); default: printf_debug("4b ID not supported on this SPI controller\n"); } return 0; } -int probe_spi_rems(struct flashchip *flash) -{ - unsigned char readarr[JEDEC_REMS_INSIZE]; - uint32_t id1, id2; - - if (spi_rems(readarr)) - return 0; - - id1 = readarr[0]; - id2 = readarr[1]; - - printf_debug("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); - - if (id1 == flash->manufacture_id && id2 == flash->model_id) { - /* Print the status register to tell the - * user about possible write protection. - */ - spi_prettyprint_status_register(flash); - - return 1; - } - - /* Test if this is a pure vendor match. */ - if (id1 == flash->manufacture_id && - GENERIC_DEVICE_ID == flash->model_id) - return 1; - - /* Test if there is any vendor ID. */ - if (GENERIC_MANUF_ID == flash->manufacture_id && - id1 != 0xff) - return 1; - - return 0; -} - -int probe_spi_res(struct flashchip *flash) -{ - unsigned char readarr[3]; - uint32_t id2; - const unsigned char allff[] = {0xff, 0xff, 0xff}; - const unsigned char all00[] = {0x00, 0x00, 0x00}; - - /* Check if RDID is usable and does not return 0xff 0xff 0xff or - * 0x00 0x00 0x00. In that case, RES is pointless. - */ - if (!spi_rdid(readarr, 3) && memcmp(readarr, allff, 3) && - memcmp(readarr, all00, 3)) { - msg_cdbg("Ignoring RES in favour of RDID.\n"); - return 0; - } - /* Check if REMS is usable and does not return 0xff 0xff or - * 0x00 0x00. In that case, RES is pointless. - */ - if (!spi_rems(readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) && - memcmp(readarr, all00, JEDEC_REMS_INSIZE)) { - msg_cdbg("Ignoring RES in favour of REMS.\n"); - return 0; - } - - if (spi_res(readarr)) - return 0; - - /* FIXME: Handle the case where RES gives a 2-byte response. */ - id2 = readarr[0]; - printf_debug("%s: id 0x%x\n", __func__, id2); - if (id2 != flash->model_id) - return 0; - - /* Print the status register to tell the - * user about possible write protection. - */ - spi_prettyprint_status_register(flash); - return 1; -} - -uint8_t spi_read_status_register(void) -{ - const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; - /* FIXME: No workarounds for driver/hardware bugs in generic code. */ - unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ - int ret; - - /* Read Status Register */ - ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); - if (ret) - fprintf(stderr, "RDSR failed!\n"); - - return readarr[0]; -} - -/* Prettyprint the status register. Common definitions. */ -void spi_prettyprint_status_register_common(uint8_t status) -{ - printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - printf_debug("Chip status register: Write Enable Latch (WEL) is " - "%sset\n", (status & (1 << 1)) ? "" : "not "); - printf_debug("Chip status register: Write In Progress (WIP/BUSY) is " - "%sset\n", (status & (1 << 0)) ? "" : "not "); -} - -/* Prettyprint the status register. Works for - * ST M25P series - * MX MX25L series - */ -void spi_prettyprint_status_register_st_m25p(uint8_t status) -{ - printf_debug("Chip status register: Status Register Write Disable " - "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); - printf_debug("Chip status register: Bit 6 is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - spi_prettyprint_status_register_common(status); -} - -void spi_prettyprint_status_register_sst25(uint8_t status) -{ - printf_debug("Chip status register: Block Protect Write Disable " - "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); - printf_debug("Chip status register: Auto Address Increment Programming " - "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); - spi_prettyprint_status_register_common(status); -} - -/* Prettyprint the status register. Works for - * SST 25VF016 - */ -void spi_prettyprint_status_register_sst25vf016(uint8_t status) -{ - const char *bpt[] = { - "none", - "1F0000H-1FFFFFH", - "1E0000H-1FFFFFH", - "1C0000H-1FFFFFH", - "180000H-1FFFFFH", - "100000H-1FFFFFH", - "all", "all" - }; - spi_prettyprint_status_register_sst25(status); - printf_debug("Resulting block protection : %s\n", - bpt[(status & 0x1c) >> 2]); -} - -void spi_prettyprint_status_register_sst25vf040b(uint8_t status) -{ - const char *bpt[] = { - "none", - "0x70000-0x7ffff", - "0x60000-0x7ffff", - "0x40000-0x7ffff", - "all blocks", "all blocks", "all blocks", "all blocks" - }; - spi_prettyprint_status_register_sst25(status); - printf_debug("Resulting block protection : %s\n", - bpt[(status & 0x1c) >> 2]); -} - -void spi_prettyprint_status_register(struct flashchip *flash) -{ - uint8_t status; - - status = spi_read_status_register(); - printf_debug("Chip status register is %02x\n", status); - switch (flash->manufacture_id) { - case ST_ID: - if (((flash->model_id & 0xff00) == 0x2000) || - ((flash->model_id & 0xff00) == 0x2500)) - spi_prettyprint_status_register_st_m25p(status); - break; - case MX_ID: - if ((flash->model_id & 0xff00) == 0x2000) - spi_prettyprint_status_register_st_m25p(status); - break; - case SST_ID: - switch (flash->model_id) { - case 0x2541: - spi_prettyprint_status_register_sst25vf016(status); - break; - case 0x8d: - case 0x258d: - spi_prettyprint_status_register_sst25vf040b(status); - break; - default: - spi_prettyprint_status_register_sst25(status); - break; - } - break; - } -} - -int spi_chip_erase_60(struct flashchip *flash) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_CE_60_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_CE_60 }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_disable_blockprotect(); - if (result) { - fprintf(stderr, "spi_disable_blockprotect failed\n"); - return result; - } - - result = spi_send_multicommand(cmds); - if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(1000 * 1000); - if (check_erased_range(flash, 0, flash->total_size * 1024)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - return 0; -} - -int spi_chip_erase_c7(struct flashchip *flash) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_CE_C7_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_disable_blockprotect(); - if (result) { - fprintf(stderr, "spi_disable_blockprotect failed\n"); - return result; - } - - result = spi_send_multicommand(cmds); - if (result) { - fprintf(stderr, "%s failed during command execution\n", __func__); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(1000 * 1000); - if (check_erased_range(flash, 0, flash->total_size * 1024)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - return 0; -} - -int spi_chip_erase_60_c7(struct flashchip *flash) -{ - int result; - result = spi_chip_erase_60(flash); - if (result) { - printf_debug("spi_chip_erase_60 failed, trying c7\n"); - result = spi_chip_erase_c7(flash); - } - return result; -} - -int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_52_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(cmds); - if (result) { - fprintf(stderr, "%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(100 * 1000); - if (check_erased_range(flash, addr, blocklen)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - return 0; -} - -/* Block size is usually - * 64k for Macronix - * 32k for SST - * 4-32k non-uniform for EON - */ -int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_D8_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(cmds); - if (result) { - fprintf(stderr, "%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(100 * 1000); - if (check_erased_range(flash, addr, blocklen)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - return 0; -} - -/* Block size is usually - * 4k for PMC - */ -int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_D7_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_BE_D7, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(cmds); - if (result) { - fprintf(stderr, "%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(100 * 1000); - if (check_erased_range(flash, addr, blocklen)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - return 0; -} - -int spi_chip_erase_d8(struct flashchip *flash) -{ - int i, rc = 0; - int total_size = flash->total_size * 1024; - int erase_size = 64 * 1024; - - spi_disable_blockprotect(); - - printf("Erasing chip: \n"); - - for (i = 0; i < total_size / erase_size; i++) { - rc = spi_block_erase_d8(flash, i * erase_size, erase_size); - if (rc) { - fprintf(stderr, "Error erasing block at 0x%x\n", i); - break; - } - } - - printf("\n"); - - return rc; -} - -/* Sector size is usually 4k, though Macronix eliteflash has 64k */ -int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_SE_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(cmds); - if (result) { - fprintf(stderr, "%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 15-800 ms, so wait in 10 ms steps. - */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(10 * 1000); - if (check_erased_range(flash, addr, blocklen)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - return 0; -} - -int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen) -{ - if ((addr != 0) || (blocklen != flash->total_size * 1024)) { - fprintf(stderr, "%s called with incorrect arguments\n", - __func__); - return -1; - } - return spi_chip_erase_60(flash); -} - -int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) -{ - if ((addr != 0) || (blocklen != flash->total_size * 1024)) { - fprintf(stderr, "%s called with incorrect arguments\n", - __func__); - return -1; - } - return spi_chip_erase_c7(flash); -} - -int spi_write_status_enable(void) -{ - const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; - int result; - - /* Send EWSR (Enable Write Status Register). */ - result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); - - if (result) - fprintf(stderr, "%s failed\n", __func__); - - return result; -} - -/* - * This is according the SST25VF016 datasheet, who knows it is more - * generic that this... - */ -int spi_write_status_register(int status) -{ - int result; - struct spi_command cmds[] = { - { - /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ - .writecnt = JEDEC_EWSR_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_EWSR }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_WRSR_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(cmds); - if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); - } - return result; -} - -int spi_byte_program(int addr, uint8_t databyte) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), databyte }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(cmds); - if (result) { - fprintf(stderr, "%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; -} - -int spi_nbyte_program(int addr, uint8_t *bytes, int len) -{ - int result; - /* FIXME: Switch to malloc based on len unless that kills speed. */ - unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { - JEDEC_BYTE_PROGRAM, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr >> 0) & 0xff, - }; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, - .writearr = cmd, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - if (!len) { - fprintf(stderr, "%s called for zero-length write\n", __func__); - return 1; - } - if (len > 256) { - fprintf(stderr, "%s called for too long a write\n", __func__); - return 1; - } - - memcpy(&cmd[4], bytes, len); - - result = spi_send_multicommand(cmds); - if (result) { - fprintf(stderr, "%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; -} - -int spi_disable_blockprotect(void) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If there is block protection in effect, unprotect it first. */ - if ((status & 0x3c) != 0) { - printf_debug("Some block protection in effect, disabling\n"); - result = spi_write_status_register(status & ~0x3c); - if (result) { - fprintf(stderr, "spi_write_status_register failed\n"); - return result; - } - } - return 0; -} - -int spi_nbyte_read(int address, uint8_t *bytes, int len) -{ - const unsigned char cmd[JEDEC_READ_OUTSIZE] = { - JEDEC_READ, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - (address >> 0) & 0xff, - }; - - /* Send Read */ - return spi_send_command(sizeof(cmd), len, cmd, bytes); -} - -/* - * Read a complete flash chip. - * Each page is read separately in chunks with a maximum size of chunksize. - */ -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) -{ - int rc = 0; - int i, j, starthere, lenhere; - int page_size = flash->page_size; - int toread; - - /* Warning: This loop has a very unusual condition and body. - * The loop needs to go through each page with at least one affected - * byte. The lowest page number is (start / page_size) since that - * division rounds down. The highest page number we want is the page - * where the last byte of the range lives. That last byte has the - * address (start + len - 1), thus the highest page number is - * (start + len - 1) / page_size. Since we want to include that last - * page as well, the loop condition uses <=. - */ - for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { - /* Byte position of the first byte in the range in this page. */ - /* starthere is an offset to the base address of the chip. */ - starthere = max(start, i * page_size); - /* Length of bytes in the range in this page. */ - lenhere = min(start + len, (i + 1) * page_size) - starthere; - for (j = 0; j < lenhere; j += chunksize) { - toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread); - if (rc) - break; - } - if (rc) - break; - } - - return rc; -} - int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].read) { fprintf(stderr, "%s called, but SPI read is unsupported on this" " hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].read(flash, buf, start, len); } -/* - * Program chip using byte programming. (SLOW!) - * This is for chips which can only handle one byte writes - * and for chips where memory mapped programming is impossible - * (e.g. due to size constraints in IT87* for over 512 kB) - */ -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) -{ - int total_size = 1024 * flash->total_size; - int i, result = 0; - - spi_disable_blockprotect(); - /* Erase first */ - printf("Erasing flash before programming... "); - if (erase_flash(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - printf("done.\n"); - for (i = 0; i < total_size; i++) { - result = spi_byte_program(i, buf[i]); - if (result) - return 1; - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(10); - } +uint32_t spi_get_valid_read_addr(void) +{ + /* Need to return BBAR for ICH chipsets. */ return 0; } /* * Program chip using page (256 bytes) programming. * Some SPI masters can't do this, they use single byte programming instead. */ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { if (!spi_programmer[spi_controller].write_256) { fprintf(stderr, "%s called, but SPI page write is unsupported " " on this hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].write_256(flash, buf); } -uint32_t spi_get_valid_read_addr(void) -{ - /* Need to return BBAR for ICH chipsets. */ - return 0; -} - -int spi_aai_write(struct flashchip *flash, uint8_t *buf) -{ - uint32_t pos = 2, size = flash->total_size * 1024; - unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; - int result; - - switch (spi_controller) { -#if INTERNAL_SUPPORT == 1 - case SPI_CONTROLLER_WBSIO: - fprintf(stderr, "%s: impossible with Winbond SPI masters," - " degrading to byte program\n", __func__); - return spi_chip_write_1(flash, buf); -#endif - default: - break; - } - if (erase_flash(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - /* FIXME: This will fail on ICH/VIA SPI. */ - result = spi_write_enable(); - if (result) - return result; - spi_send_command(6, 0, w, NULL); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ - while (pos < size) { - w[1] = buf[pos++]; - w[2] = buf[pos++]; - spi_send_command(3, 0, w, NULL); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ - } - spi_write_disable(); - return 0; -} diff --git a/spi25.c b/spi25.c new file mode 100644 index 0000000..624e22d --- /dev/null +++ b/spi25.c @@ -0,0 +1,964 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Contains the generic SPI framework + */ + +#include +#include "flash.h" +#include "flashchips.h" +#include "chipdrivers.h" +#include "spi.h" + +void spi_prettyprint_status_register(struct flashchip *flash); + +int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + struct spi_command cmd[] = { + { + .writecnt = writecnt, + .readcnt = readcnt, + .writearr = writearr, + .readarr = readarr, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + return spi_send_multicommand(cmd); +} + +int default_spi_send_multicommand(struct spi_command *cmds) +{ + int result = 0; + for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { + result = spi_send_command(cmds->writecnt, cmds->readcnt, + cmds->writearr, cmds->readarr); + } + return result; +} + +static int spi_rdid(unsigned char *readarr, int bytes) +{ + const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; + int ret; + int i; + + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); + if (ret) + return ret; + printf_debug("RDID returned"); + for (i = 0; i < bytes; i++) + printf_debug(" 0x%02x", readarr[i]); + printf_debug(". "); + return 0; +} + +static int spi_rems(unsigned char *readarr) +{ + unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; + uint32_t readaddr; + int ret; + + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + if (ret == SPI_INVALID_ADDRESS) { + /* Find the lowest even address allowed for reads. */ + readaddr = (spi_get_valid_read_addr() + 1) & ~1; + cmd[1] = (readaddr >> 16) & 0xff, + cmd[2] = (readaddr >> 8) & 0xff, + cmd[3] = (readaddr >> 0) & 0xff, + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + } + if (ret) + return ret; + printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]); + return 0; +} + +static int spi_res(unsigned char *readarr) +{ + unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; + uint32_t readaddr; + int ret; + + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + if (ret == SPI_INVALID_ADDRESS) { + /* Find the lowest even address allowed for reads. */ + readaddr = (spi_get_valid_read_addr() + 1) & ~1; + cmd[1] = (readaddr >> 16) & 0xff, + cmd[2] = (readaddr >> 8) & 0xff, + cmd[3] = (readaddr >> 0) & 0xff, + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + } + if (ret) + return ret; + printf_debug("RES returned %02x. ", readarr[0]); + return 0; +} + +int spi_write_enable(void) +{ + const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; + int result; + + /* Send WREN (Write Enable) */ + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + + if (result) + fprintf(stderr, "%s failed\n", __func__); + + return result; +} + +int spi_write_disable(void) +{ + const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; + + /* Send WRDI (Write Disable) */ + return spi_send_command(sizeof(cmd), 0, cmd, NULL); +} + +int probe_spi_rdid_generic(struct flashchip *flash, int bytes) +{ + unsigned char readarr[4]; + uint32_t id1; + uint32_t id2; + + if (spi_rdid(readarr, bytes)) + return 0; + + if (!oddparity(readarr[0])) + printf_debug("RDID byte 0 parity violation. "); + + /* Check if this is a continuation vendor ID */ + if (readarr[0] == 0x7f) { + if (!oddparity(readarr[1])) + printf_debug("RDID byte 1 parity violation. "); + id1 = (readarr[0] << 8) | readarr[1]; + id2 = readarr[2]; + if (bytes > 3) { + id2 <<= 8; + id2 |= readarr[3]; + } + } else { + id1 = readarr[0]; + id2 = (readarr[1] << 8) | readarr[2]; + } + + printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); + + if (id1 == flash->manufacture_id && id2 == flash->model_id) { + /* Print the status register to tell the + * user about possible write protection. + */ + spi_prettyprint_status_register(flash); + + return 1; + } + + /* Test if this is a pure vendor match. */ + if (id1 == flash->manufacture_id && + GENERIC_DEVICE_ID == flash->model_id) + return 1; + + /* Test if there is any vendor ID. */ + if (GENERIC_MANUF_ID == flash->manufacture_id && + id1 != 0xff) + return 1; + + return 0; +} + +int probe_spi_rdid(struct flashchip *flash) +{ + return probe_spi_rdid_generic(flash, 3); +} + +/* support 4 bytes flash ID */ +int probe_spi_rems(struct flashchip *flash) +{ + unsigned char readarr[JEDEC_REMS_INSIZE]; + uint32_t id1, id2; + + if (spi_rems(readarr)) + return 0; + + id1 = readarr[0]; + id2 = readarr[1]; + + printf_debug("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); + + if (id1 == flash->manufacture_id && id2 == flash->model_id) { + /* Print the status register to tell the + * user about possible write protection. + */ + spi_prettyprint_status_register(flash); + + return 1; + } + + /* Test if this is a pure vendor match. */ + if (id1 == flash->manufacture_id && + GENERIC_DEVICE_ID == flash->model_id) + return 1; + + /* Test if there is any vendor ID. */ + if (GENERIC_MANUF_ID == flash->manufacture_id && + id1 != 0xff) + return 1; + + return 0; +} + +int probe_spi_res(struct flashchip *flash) +{ + unsigned char readarr[3]; + uint32_t id2; + const unsigned char allff[] = {0xff, 0xff, 0xff}; + const unsigned char all00[] = {0x00, 0x00, 0x00}; + + /* Check if RDID is usable and does not return 0xff 0xff 0xff or + * 0x00 0x00 0x00. In that case, RES is pointless. + */ + if (!spi_rdid(readarr, 3) && memcmp(readarr, allff, 3) && + memcmp(readarr, all00, 3)) { + msg_cdbg("Ignoring RES in favour of RDID.\n"); + return 0; + } + /* Check if REMS is usable and does not return 0xff 0xff or + * 0x00 0x00. In that case, RES is pointless. + */ + if (!spi_rems(readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) && + memcmp(readarr, all00, JEDEC_REMS_INSIZE)) { + msg_cdbg("Ignoring RES in favour of REMS.\n"); + return 0; + } + + if (spi_res(readarr)) + return 0; + + /* FIXME: Handle the case where RES gives a 2-byte response. */ + id2 = readarr[0]; + printf_debug("%s: id 0x%x\n", __func__, id2); + if (id2 != flash->model_id) + return 0; + + /* Print the status register to tell the + * user about possible write protection. + */ + spi_prettyprint_status_register(flash); + return 1; +} + +uint8_t spi_read_status_register(void) +{ + const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; + /* FIXME: No workarounds for driver/hardware bugs in generic code. */ + unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ + int ret; + + /* Read Status Register */ + ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + if (ret) + fprintf(stderr, "RDSR failed!\n"); + + return readarr[0]; +} + +/* Prettyprint the status register. Common definitions. */ +void spi_prettyprint_status_register_common(uint8_t status) +{ + printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is " + "%sset\n", (status & (1 << 5)) ? "" : "not "); + printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is " + "%sset\n", (status & (1 << 4)) ? "" : "not "); + printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is " + "%sset\n", (status & (1 << 3)) ? "" : "not "); + printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is " + "%sset\n", (status & (1 << 2)) ? "" : "not "); + printf_debug("Chip status register: Write Enable Latch (WEL) is " + "%sset\n", (status & (1 << 1)) ? "" : "not "); + printf_debug("Chip status register: Write In Progress (WIP/BUSY) is " + "%sset\n", (status & (1 << 0)) ? "" : "not "); +} + +/* Prettyprint the status register. Works for + * ST M25P series + * MX MX25L series + */ +void spi_prettyprint_status_register_st_m25p(uint8_t status) +{ + printf_debug("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + printf_debug("Chip status register: Bit 6 is " + "%sset\n", (status & (1 << 6)) ? "" : "not "); + spi_prettyprint_status_register_common(status); +} + +void spi_prettyprint_status_register_sst25(uint8_t status) +{ + printf_debug("Chip status register: Block Protect Write Disable " + "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); + printf_debug("Chip status register: Auto Address Increment Programming " + "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); + spi_prettyprint_status_register_common(status); +} + +/* Prettyprint the status register. Works for + * SST 25VF016 + */ +void spi_prettyprint_status_register_sst25vf016(uint8_t status) +{ + const char *bpt[] = { + "none", + "1F0000H-1FFFFFH", + "1E0000H-1FFFFFH", + "1C0000H-1FFFFFH", + "180000H-1FFFFFH", + "100000H-1FFFFFH", + "all", "all" + }; + spi_prettyprint_status_register_sst25(status); + printf_debug("Resulting block protection : %s\n", + bpt[(status & 0x1c) >> 2]); +} + +void spi_prettyprint_status_register_sst25vf040b(uint8_t status) +{ + const char *bpt[] = { + "none", + "0x70000-0x7ffff", + "0x60000-0x7ffff", + "0x40000-0x7ffff", + "all blocks", "all blocks", "all blocks", "all blocks" + }; + spi_prettyprint_status_register_sst25(status); + printf_debug("Resulting block protection : %s\n", + bpt[(status & 0x1c) >> 2]); +} + +void spi_prettyprint_status_register(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + printf_debug("Chip status register is %02x\n", status); + switch (flash->manufacture_id) { + case ST_ID: + if (((flash->model_id & 0xff00) == 0x2000) || + ((flash->model_id & 0xff00) == 0x2500)) + spi_prettyprint_status_register_st_m25p(status); + break; + case MX_ID: + if ((flash->model_id & 0xff00) == 0x2000) + spi_prettyprint_status_register_st_m25p(status); + break; + case SST_ID: + switch (flash->model_id) { + case 0x2541: + spi_prettyprint_status_register_sst25vf016(status); + break; + case 0x8d: + case 0x258d: + spi_prettyprint_status_register_sst25vf040b(status); + break; + default: + spi_prettyprint_status_register_sst25(status); + break; + } + break; + } +} + +int spi_chip_erase_60(struct flashchip *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_60_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_60 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_disable_blockprotect(); + if (result) { + fprintf(stderr, "spi_disable_blockprotect failed\n"); + return result; + } + + result = spi_send_multicommand(cmds); + if (result) { + fprintf(stderr, "%s failed during command execution\n", + __func__); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 1-85 s, so wait in 1 s steps. + */ + /* FIXME: We assume spi_read_status_register will never fail. */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(1000 * 1000); + if (check_erased_range(flash, 0, flash->total_size * 1024)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + return 0; +} + +int spi_chip_erase_c7(struct flashchip *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_C7_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_disable_blockprotect(); + if (result) { + fprintf(stderr, "spi_disable_blockprotect failed\n"); + return result; + } + + result = spi_send_multicommand(cmds); + if (result) { + fprintf(stderr, "%s failed during command execution\n", __func__); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 1-85 s, so wait in 1 s steps. + */ + /* FIXME: We assume spi_read_status_register will never fail. */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(1000 * 1000); + if (check_erased_range(flash, 0, flash->total_size * 1024)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + return 0; +} + +int spi_chip_erase_60_c7(struct flashchip *flash) +{ + int result; + result = spi_chip_erase_60(flash); + if (result) { + printf_debug("spi_chip_erase_60 failed, trying c7\n"); + result = spi_chip_erase_c7(flash); + } + return result; +} + +int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(cmds); + if (result) { + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(100 * 1000); + if (check_erased_range(flash, addr, blocklen)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + return 0; +} + +/* Block size is usually + * 64k for Macronix + * 32k for SST + * 4-32k non-uniform for EON + */ +int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(cmds); + if (result) { + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(100 * 1000); + if (check_erased_range(flash, addr, blocklen)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + return 0; +} + +/* Block size is usually + * 4k for PMC + */ +int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D7_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_D7, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(cmds); + if (result) { + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(100 * 1000); + if (check_erased_range(flash, addr, blocklen)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + return 0; +} + +int spi_chip_erase_d8(struct flashchip *flash) +{ + int i, rc = 0; + int total_size = flash->total_size * 1024; + int erase_size = 64 * 1024; + + spi_disable_blockprotect(); + + printf("Erasing chip: \n"); + + for (i = 0; i < total_size / erase_size; i++) { + rc = spi_block_erase_d8(flash, i * erase_size, erase_size); + if (rc) { + fprintf(stderr, "Error erasing block at 0x%x\n", i); + break; + } + } + + printf("\n"); + + return rc; +} + +/* Sector size is usually 4k, though Macronix eliteflash has 64k */ +int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(cmds); + if (result) { + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(10 * 1000); + if (check_erased_range(flash, addr, blocklen)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + return 0; +} + +int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +{ + if ((addr != 0) || (blocklen != flash->total_size * 1024)) { + fprintf(stderr, "%s called with incorrect arguments\n", + __func__); + return -1; + } + return spi_chip_erase_60(flash); +} + +int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +{ + if ((addr != 0) || (blocklen != flash->total_size * 1024)) { + fprintf(stderr, "%s called with incorrect arguments\n", + __func__); + return -1; + } + return spi_chip_erase_c7(flash); +} + +int spi_write_status_enable(void) +{ + const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; + int result; + + /* Send EWSR (Enable Write Status Register). */ + result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + + if (result) + fprintf(stderr, "%s failed\n", __func__); + + return result; +} + +/* + * This is according the SST25VF016 datasheet, who knows it is more + * generic that this... + */ +int spi_write_status_register(int status) +{ + int result; + struct spi_command cmds[] = { + { + /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ + .writecnt = JEDEC_EWSR_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_EWSR }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_WRSR_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(cmds); + if (result) { + fprintf(stderr, "%s failed during command execution\n", + __func__); + } + return result; +} + +int spi_byte_program(int addr, uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), databyte }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(cmds); + if (result) { + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +int spi_nbyte_program(int addr, uint8_t *bytes, int len) +{ + int result; + /* FIXME: Switch to malloc based on len unless that kills speed. */ + unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { + JEDEC_BYTE_PROGRAM, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff, + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + if (!len) { + fprintf(stderr, "%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + fprintf(stderr, "%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[4], bytes, len); + + result = spi_send_multicommand(cmds); + if (result) { + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +int spi_disable_blockprotect(void) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If there is block protection in effect, unprotect it first. */ + if ((status & 0x3c) != 0) { + printf_debug("Some block protection in effect, disabling\n"); + result = spi_write_status_register(status & ~0x3c); + if (result) { + fprintf(stderr, "spi_write_status_register failed\n"); + return result; + } + } + return 0; +} + +int spi_nbyte_read(int address, uint8_t *bytes, int len) +{ + const unsigned char cmd[JEDEC_READ_OUTSIZE] = { + JEDEC_READ, + (address >> 16) & 0xff, + (address >> 8) & 0xff, + (address >> 0) & 0xff, + }; + + /* Send Read */ + return spi_send_command(sizeof(cmd), len, cmd, bytes); +} + +/* + * Read a complete flash chip. + * Each page is read separately in chunks with a maximum size of chunksize. + */ +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +{ + int rc = 0; + int i, j, starthere, lenhere; + int page_size = flash->page_size; + int toread; + + /* Warning: This loop has a very unusual condition and body. + * The loop needs to go through each page with at least one affected + * byte. The lowest page number is (start / page_size) since that + * division rounds down. The highest page number we want is the page + * where the last byte of the range lives. That last byte has the + * address (start + len - 1), thus the highest page number is + * (start + len - 1) / page_size. Since we want to include that last + * page as well, the loop condition uses <=. + */ + for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { + /* Byte position of the first byte in the range in this page. */ + /* starthere is an offset to the base address of the chip. */ + starthere = max(start, i * page_size); + /* Length of bytes in the range in this page. */ + lenhere = min(start + len, (i + 1) * page_size) - starthere; + for (j = 0; j < lenhere; j += chunksize) { + toread = min(chunksize, lenhere - j); + rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread); + if (rc) + break; + } + if (rc) + break; + } + + return rc; +} + +/* + * Program chip using byte programming. (SLOW!) + * This is for chips which can only handle one byte writes + * and for chips where memory mapped programming is impossible + * (e.g. due to size constraints in IT87* for over 512 kB) + */ +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) +{ + int total_size = 1024 * flash->total_size; + int i, result = 0; + + spi_disable_blockprotect(); + /* Erase first */ + printf("Erasing flash before programming... "); + if (erase_flash(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + printf("done.\n"); + for (i = 0; i < total_size; i++) { + result = spi_byte_program(i, buf[i]); + if (result) + return 1; + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(10); + } + + return 0; +} + +int spi_aai_write(struct flashchip *flash, uint8_t *buf) +{ + uint32_t pos = 2, size = flash->total_size * 1024; + unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; + int result; + + switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 + case SPI_CONTROLLER_WBSIO: + fprintf(stderr, "%s: impossible with Winbond SPI masters," + " degrading to byte program\n", __func__); + return spi_chip_write_1(flash, buf); +#endif + default: + break; + } + if (erase_flash(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + /* FIXME: This will fail on ICH/VIA SPI. */ + result = spi_write_enable(); + if (result) + return result; + spi_send_command(6, 0, w, NULL); + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ + while (pos < size) { + w[1] = buf[pos++]; + w[2] = buf[pos++]; + spi_send_command(3, 0, w, NULL); + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ + } + spi_write_disable(); + return 0; +} diff --git a/sst28sf040.c b/sst28sf040.c index f253e39..bbb9d56 100644 --- a/sst28sf040.c +++ b/sst28sf040.c @@ -11,26 +11,27 @@ * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "flash.h" +#include "chipdrivers.h" #define AUTO_PG_ERASE1 0x20 #define AUTO_PG_ERASE2 0xD0 #define AUTO_PGRM 0x10 #define CHIP_ERASE 0x30 #define RESET 0xFF #define READ_ID 0x90 static void protect_28sf040(chipaddr bios) { chip_readb(bios + 0x1823); chip_readb(bios + 0x1820); chip_readb(bios + 0x1822); diff --git a/sst_fwhub.c b/sst_fwhub.c index 75d9e05..9819cee 100644 --- a/sst_fwhub.c +++ b/sst_fwhub.c @@ -15,26 +15,27 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* Adapted from the Intel FW hub stuff for 82802ax parts. */ #include #include #include "flash.h" +#include "chipdrivers.h" // I need that Berkeley bit-map printer void print_sst_fwhub_status(uint8_t status) { printf("%s", status & 0x80 ? "Ready:" : "Busy:"); printf("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:"); printf("%s", status & 0x20 ? "BE ERROR:" : "BE OK:"); printf("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:"); printf("%s", status & 0x8 ? "VP ERR:" : "VPP OK:"); printf("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:"); printf("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:"); } diff --git a/w39v040c.c b/w39v040c.c index 853419a..20e53fa 100644 --- a/w39v040c.c +++ b/w39v040c.c @@ -9,26 +9,27 @@ * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "flash.h" +#include "chipdrivers.h" int probe_w39v040c(struct flashchip *flash) { chipaddr bios = flash->virtual_memory; int result = probe_jedec(flash); uint8_t lock; if (!result) return result; chip_writeb(0xAA, bios + 0x5555); programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); diff --git a/w39v080fa.c b/w39v080fa.c index 8e846dc..0163766 100644 --- a/w39v080fa.c +++ b/w39v080fa.c @@ -9,26 +9,27 @@ * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "flash.h" +#include "chipdrivers.h" static int unlock_block_winbond_fwhub(struct flashchip *flash, int offset) { chipaddr wrprotect = flash->virtual_registers + offset + 2; uint8_t locking; printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, chip_readb(wrprotect)); locking = chip_readb(wrprotect); switch (locking & 0x7) { case 0: printf_debug("Full Access.\n"); diff --git a/wbsio_spi.c b/wbsio_spi.c index 922aff1..5fe34f9 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -10,26 +10,28 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "flash.h" +#include "hwaccess.h" +#include "chipdrivers.h" #include "spi.h" #define WBSIO_PORT1 0x2e #define WBSIO_PORT2 0x4e static uint16_t wbsio_spibase = 0; static uint16_t wbsio_get_spibase(uint16_t port) { uint8_t id; uint16_t flashport = 0; w836xx_ext_enter(port);