>
> Another related thing is an optimization that I have in mind since ever
> I used flashrom: Selection of the biggest possible erase block size.
> Currently, if we erase/write say 16 blocks of 4KiB, we waste a lot of
> time because most chips would erase a 64KiB block much faster. If we
> ever add something like this, I guess it would be easier with approach
> 1). But maybe it'd be so invasive that it doesn't matter much...
I'd like this as well, and agree that it would be easier with the first approach. As far as invasiveness goes, the tricky part IMO is updating portions of read logic to deal with unaligned layout regions to ensure data outside the targeted region is restored, which requires knowing the eraseblock size in advance. Otherwise you end up with hacks like this:
https://chromium-review.googlesource.com/c/240176/