September 2013 - flashrom - mail.coreboot.org

Flashrom stuck using 100% cpu while probing for a chip
by GatoLoko April 28, 2014

April 28, 2014

I've tried to run flashrom -V to see if it could identify the chip on my new board (AsRock M3A-GLAN), and it got stuck while probing for the first chip. I've tried commenting out that specific chip (AMIC A25L05PT) and then it gets stuck on the next one. Then commented out all AMIC chips, and it got stuck on the next one (the first ATMEL on the list) I've tried with an older flashrom (0.9.2-r1141). It skipped some AMD chips, then got stuck on AMIC again. Talked with "tlt" and "stefanct" on irc and they asked for a strace and a gdb backtrace. Strace produced no results. Gdb log is attached. "stefanct" tried and reproduced it on a machine with nicintel_spi, but warned it was with an unsupported nic: http://paste.flashrom.org/view.php?id=738 -- GatoLoko

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[PATCH] Refactor spi_read_status_register usage
by Carl-Daniel Hailfinger March 8, 2014

March 8, 2014

spi_read_status_register() is used in open-coded loops everywhere just to check if SPI_SR_WIP bit cleared. The logic is missing a timeout detection, and we can save quite a lot of code by introducing a function which waits until SPI_SR_WIP is cleared or a timeout is reached. Untested. May explode. Unfinished. More functions need to be converted to the new style. Will change behaviour if the chip is too slow or hangs. Should prevent flashrom from hanging without any visible output. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_rdsr_refactor/spi25.c =================================================================== --- flashrom-spi_rdsr_refactor/spi25.c (Revision 1653) +++ flashrom-spi_rdsr_refactor/spi25.c (Arbeitskopie) @@ -328,14 +328,9 @@ __func__); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 120 * 1000 * 1000, JEDEC_CE_60); + return result; } int spi_chip_erase_62(struct flashctx *flash) @@ -365,14 +360,9 @@ __func__); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 2-5 s, so wait in 100 ms steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 120 * 1000 * 1000, JEDEC_CE_62); + return result; } int spi_chip_erase_c7(struct flashctx *flash) @@ -401,14 +391,9 @@ msg_cerr("%s failed during command execution\n", __func__); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 120 * 1000 * 1000, JEDEC_CE_C7); + return result; } int spi_block_erase_52(struct flashctx *flash, unsigned int addr, @@ -444,13 +429,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_52); + return result; } /* Block size is usually @@ -491,13 +472,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_D8); + return result; } /* Block size is usually @@ -536,13 +513,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_D7); + return result; } /* Sector size is usually 4k, though Macronix eliteflash has 64k */ @@ -579,13 +552,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 15-800 ms, so wait in 10 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_SE); + return result; } int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) @@ -619,13 +588,9 @@ msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 10 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_50); + return result; } int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) @@ -659,13 +624,9 @@ msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 8 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_81); + return result; } int spi_block_erase_60(struct flashctx *flash, unsigned int addr, Index: flashrom-spi_rdsr_refactor/spi25_statusreg.c =================================================================== --- flashrom-spi_rdsr_refactor/spi25_statusreg.c (Revision 1653) +++ flashrom-spi_rdsr_refactor/spi25_statusreg.c (Arbeitskopie) @@ -43,7 +43,6 @@ static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode) { int result; - int i = 0; /* * WRSR requires either EWSR or WREN depending on chip type. * The code below relies on the fact hat EWSR and WREN have the same @@ -78,17 +77,10 @@ /* WRSR performs a self-timed erase before the changes take effect. * This may take 50-85 ms in most cases, and some chips apparently * allow running RDSR only once. Therefore pick an initial delay of - * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. + * 100 ms, then wait until a total of 5 s have elapsed. */ programmer_delay(100 * 1000); - while (spi_read_status_register(flash) & SPI_SR_WIP) { - if (++i > 490) { - msg_cerr("Error: WIP bit after WRSR never cleared\n"); - return TIMEOUT_ERROR; - } - programmer_delay(10 * 1000); - } - return 0; + return spi_wait_status_register_ready(flash, 4900 * 1000, JEDEC_WRSR); } int spi_write_status_register(struct flashctx *flash, int status) @@ -108,6 +100,28 @@ return ret; } +/* timeout is specified in usecs. */ +int spi_wait_status_register_ready(struct flashctx *flash, int timeout, uint8_t opcode) +{ + /* At least 1 usec between iterations. */ + int single_delay = (timeout / 100) ? : 1; + int elapsed = 0; + int halftime = 0; + + while (spi_read_status_register(flash) & SPI_SR_WIP) { + elapsed += single_delay; + if ((elapsed > timeout / 2) && !halftime) { + msg_cdbg("Debug: WIP bit after %02x didn't clear within %i us.\n", opcode, timeout/2); + } + if (elapsed >= timeout) { + msg_cerr("Error: WIP bit after %02x didn't clear within %i us.\n", opcode, timeout); + return TIMEOUT_ERROR; + } + programmer_delay(single_delay); + } + return 0; +} + uint8_t spi_read_status_register(struct flashctx *flash) { static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; Index: flashrom-spi_rdsr_refactor/chipdrivers.h =================================================================== --- flashrom-spi_rdsr_refactor/chipdrivers.h (Revision 1653) +++ flashrom-spi_rdsr_refactor/chipdrivers.h (Arbeitskopie) @@ -60,6 +60,7 @@ /* spi25_statusreg.c */ uint8_t spi_read_status_register(struct flashctx *flash); +int spi_wait_status_register_ready(struct flashctx *flash, int timeout, uint8_t opcode); int spi_write_status_register(struct flashctx *flash, int status); int spi_prettyprint_status_register_plain(struct flashctx *flash); int spi_prettyprint_status_register_default_bp1(struct flashctx *flash); -- http://www.hailfinger.org/

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Re: [flashrom] Raspberry Pi Pm25LD010 output files
by Stefan Tauner Nov. 26, 2013

Nov. 26, 2013

On Sat, 7 Sep 2013 02:17:27 +0300 Vasile Ceteras <vasileceteras(a)gmail.com> wrote: > A million thanks for this awesome tool, it worked like a charm! > Vasile Hello Vasile, thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Fixup and remove exit from register_undo_mmio_write
by Niklas Söderlund Nov. 13, 2013

Nov. 13, 2013

This patch series can be squashed into one path, but for easier review I send it as I developed it. Let me know if you want a squashed version.

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[PATCH] Return error if malloc fail for undo_pci_write
by Niklas Söderlund Nov. 13, 2013

Nov. 13, 2013

All callers modified to handle and propagate return codes instead of relaying on the exit call. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- atahpt.c | 3 +- chipset_enable.c | 103 +++++++++++++++++++++++++++++++++++++------------------ drkaiser.c | 3 +- gfxnvidia.c | 3 +- pcidev.c | 21 +++++++++--- 5 files changed, 93 insertions(+), 40 deletions(-) diff --git a/atahpt.c b/atahpt.c index 242e14a..8ba9c9b 100644 --- a/atahpt.c +++ b/atahpt.c @@ -75,7 +75,8 @@ int atahpt_init(void) /* Enable flash access. */ reg32 = pci_read_long(dev, REG_FLASH_ACCESS); reg32 |= (1 << 24); - rpci_write_long(dev, REG_FLASH_ACCESS, reg32); + if (rpci_write_long(dev, REG_FLASH_ACCESS, reg32)) + return 1; register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); diff --git a/chipset_enable.c b/chipset_enable.c index c85db73..2a93c7c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -51,7 +51,8 @@ static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) */ tmp = pci_read_byte(dev, 0x47); tmp |= 0x46; - rpci_write_byte(dev, 0x47, tmp); + if (rpci_write_byte(dev, 0x47, tmp)) + return ERROR_FATAL; return 0; } @@ -88,7 +89,8 @@ static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) tmp = pci_read_byte(dev, 0xd0); tmp |= 0xf8; - rpci_write_byte(dev, 0xd0, tmp); + if (rpci_write_byte(dev, 0xd0, tmp)) + return ERROR_FATAL; return 0; } @@ -103,7 +105,9 @@ static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name) new = pci_read_byte(dev, SIS_MAPREG); new &= (~0x04); /* No idea why we clear bit 2. */ new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */ - rpci_write_byte(dev, SIS_MAPREG, new); + if (rpci_write_byte(dev, SIS_MAPREG, new)) + return ERROR_FATAL; + newer = pci_read_byte(dev, SIS_MAPREG); if (newer != new) { /* FIXME: share this with other code? */ msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", @@ -193,7 +197,9 @@ static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t di new = pci_read_byte(sbdev, SIS_REG); new &= (~dis_mask); new |= en_mask; - rpci_write_byte(sbdev, SIS_REG, new); + if (rpci_write_byte(sbdev, SIS_REG, new)) + return ERROR_FATAL; + newer = pci_read_byte(sbdev, SIS_REG); if (newer != new) { /* FIXME: share this with other code? */ msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name); @@ -250,7 +256,8 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name) if (new == old) return 0; - rpci_write_word(dev, xbcs, new); + if (rpci_write_word(dev, xbcs, new)) + return ERROR_FATAL; if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */ msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name); @@ -291,7 +298,8 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, uint8_t bios_ /* Only write the register if it's necessary */ if (wanted != old) { - rpci_write_byte(dev, bios_cntl, wanted); + if (rpci_write_byte(dev, bios_cntl, wanted)) + return ERROR_FATAL; new = pci_read_byte(dev, bios_cntl); } else new = old; @@ -369,8 +377,10 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name, en msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to " "0x%012" PRIx64 " for top 16 MB.", fwh_idsel_old, fwh_idsel); - rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); - rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); + if (rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff)) + return ERROR_FATAL; + if (rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff)) + return ERROR_FATAL; /* FIXME: Decode settings are not changed. */ } else if (idsel) { msg_perr("Error: fwh_idsel= specified, but no value given.\n"); @@ -514,7 +524,8 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) new = old & ~1; if (new != old) - rpci_write_byte(dev, 0xd9, new); + if (rpci_write_byte(dev, 0xd9, new)) + return ERROR_FATAL; internal_buses_supported = BUS_FWH; return 0; @@ -537,7 +548,8 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); new = old & ~1; if (new != old) - rpci_write_byte(dev, 0xd9, new); + if (rpci_write_byte(dev, 0xd9, new)) + return ERROR_FATAL; /* Get physical address of Root Complex Register Block */ tmp = pci_read_long(dev, 0xf0) & 0xffffc000; @@ -745,7 +757,8 @@ static int via_no_byte_merge(struct pci_dev *dev, const char *name) if (val & 0x40) { msg_pdbg("Disabling byte merging\n"); val &= ~0x40; - rpci_write_byte(dev, 0x71, val); + if (rpci_write_byte(dev, 0x71, val)) + return ERROR_FATAL; } return NOT_DONE_YET; /* need to find south bridge, too */ } @@ -755,12 +768,14 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name) uint8_t val; /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */ - rpci_write_byte(dev, 0x41, 0x7f); + if (rpci_write_byte(dev, 0x41, 0x7f)) + return ERROR_FATAL; /* ROM write enable */ val = pci_read_byte(dev, 0x40); val |= 0x10; - rpci_write_byte(dev, 0x40, val); + if (rpci_write_byte(dev, 0x40, val)) + return ERROR_FATAL; if (pci_read_byte(dev, 0x40) != val) { msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name); @@ -771,7 +786,8 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name) /* All memory cycles, not just ROM ones, go to LPC. */ val = pci_read_byte(dev, 0x59); val &= ~0x80; - rpci_write_byte(dev, 0x59, val); + if (rpci_write_byte(dev, 0x59, val)) + return ERROR_FATAL; } return 0; @@ -866,12 +882,14 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name) reg8 |= LOWER_ROM_ADDRESS_RANGE; reg8 |= UPPER_ROM_ADDRESS_RANGE; reg8 |= ROM_WRITE_ENABLE; - rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); + if (rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8)) + return ERROR_FATAL; /* Set positive decode on ROM. */ reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2); reg8 |= BIOS_ROM_POSITIVE_DECODE; - rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8); + if (rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8)) + return ERROR_FATAL; reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG); if (reg8 & CS5530_ISA_MASTER) { @@ -936,7 +954,8 @@ static int enable_flash_sc1100(struct pci_dev *dev, const char *name) #define SC_REG 0x52 uint8_t new; - rpci_write_byte(dev, SC_REG, 0xee); + if (rpci_write_byte(dev, SC_REG, 0xee)) + return ERROR_FATAL; new = pci_read_byte(dev, SC_REG); @@ -965,7 +984,8 @@ static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t d old = pci_read_byte(dev, AMD_MAPREG); new = old | decode_val; if (new != old) { - rpci_write_byte(dev, AMD_MAPREG, new); + if (rpci_write_byte(dev, AMD_MAPREG, new)) + return ERROR_FATAL; if (pci_read_byte(dev, AMD_MAPREG) != new) { msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", AMD_MAPREG, new, name); @@ -978,7 +998,8 @@ static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t d new = old | 0x01; if (new == old) return 0; - rpci_write_byte(dev, AMD_ENREG, new); + if (rpci_write_byte(dev, AMD_ENREG, new)) + return ERROR_FATAL; if (pci_read_byte(dev, AMD_ENREG) != new) { msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", @@ -1030,7 +1051,8 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) (prot & 0xfffff800), (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); prot &= 0xfffffffc; - rpci_write_byte(dev, reg, prot); + if (rpci_write_byte(dev, reg, prot)) + return ERROR_FATAL; prot = pci_read_long(dev, reg); if (prot & 0x3) msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n", @@ -1092,7 +1114,9 @@ static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name) if (new == old) return 0; - rpci_write_byte(dev, 0x6d, new); + if (rpci_write_byte(dev, 0x6d, new)) + return ERROR_FATAL; + if (pci_read_byte(dev, 0x6d) != new) { msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name); return 1; @@ -1102,7 +1126,9 @@ static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name) static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) { - rpci_write_byte(dev, 0x92, 0); + if (rpci_write_byte(dev, 0x92, 0)) + return ERROR_FATAL; + if (enable_flash_nvidia_common(dev, name)) return ERROR_NONFATAL; else @@ -1124,7 +1150,8 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) err++; } else { msg_pdbg("Unlocking protection in register 0x%02x... ", reg); - rpci_write_byte(dev, reg, segctrl & 0xF0); + if (rpci_write_byte(dev, reg, segctrl & 0xF0)) + return ERROR_FATAL; segctrl = pci_read_byte(dev, reg); if ((segctrl & 0x3) != 0x0) { @@ -1148,7 +1175,8 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) continue; } msg_pdbg("Unlocking protection in register 0x%02x... ", reg); - rpci_write_long(dev, reg, 0x00000000); + if (rpci_write_long(dev, reg, 0x00000000)) + return ERROR_FATAL; segctrl = pci_read_long(dev, reg); if ((segctrl & 0x33333333) != 0x00000000) { @@ -1168,7 +1196,8 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) old = pci_read_byte(dev, reg); new = old | 0xC0; if (new != old) { - rpci_write_byte(dev, reg, new); + if (rpci_write_byte(dev, reg, new)) + return ERROR_FATAL; if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */ msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name); err++; @@ -1218,12 +1247,14 @@ static int enable_flash_sb400(struct pci_dev *dev, const char *name) /* Enable some SMBus stuff. */ tmp = pci_read_byte(smbusdev, 0x79); tmp |= 0x01; - rpci_write_byte(smbusdev, 0x79, tmp); + if (rpci_write_byte(smbusdev, 0x79, tmp)) + return ERROR_FATAL; /* Change southbridge. */ tmp = pci_read_byte(dev, 0x48); tmp |= 0x21; - rpci_write_byte(dev, 0x48, tmp); + if (rpci_write_byte(dev, 0x48, tmp)) + return ERROR_FATAL; /* Now become a bit silly. */ tmp = INB(0xc6f); @@ -1245,13 +1276,16 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name) /* Set the 0-16 MB enable bits. */ val = pci_read_byte(dev, 0x88); val |= 0xff; /* 256K */ - rpci_write_byte(dev, 0x88, val); + if (rpci_write_byte(dev, 0x88, val)) + return ERROR_FATAL; val = pci_read_byte(dev, 0x8c); val |= 0xff; /* 1M */ - rpci_write_byte(dev, 0x8c, val); + if (rpci_write_byte(dev, 0x8c, val)) + return ERROR_FATAL; wordval = pci_read_word(dev, 0x90); wordval |= 0x7fff; /* 16M */ - rpci_write_word(dev, 0x90, wordval); + if (rpci_write_word(dev, 0x90, wordval)) + return ERROR_FATAL; if (enable_flash_nvidia_common(dev, name)) return ERROR_NONFATAL; @@ -1306,7 +1340,8 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) #if 0 val |= (1 << 6); val &= ~(1 << 5); - rpci_write_byte(dev, 0x8a, val); + if (rpci_write_byte(dev, 0x8a, val)) + return ERROR_FATAL; #endif if (mcp6x_spi_init(want_spi)) @@ -1329,11 +1364,13 @@ static int enable_flash_ht1000(struct pci_dev *dev, const char *name) /* Set the 4MB enable bit. */ val = pci_read_byte(dev, 0x41); val |= 0x0e; - rpci_write_byte(dev, 0x41, val); + if (rpci_write_byte(dev, 0x41, val)) + return ERROR_FATAL; val = pci_read_byte(dev, 0x43); val |= (1 << 4); - rpci_write_byte(dev, 0x43, val); + if (rpci_write_byte(dev, 0x43, val)) + return ERROR_FATAL; return 0; } diff --git a/drkaiser.c b/drkaiser.c index 0cf1fdb..407bf1a 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -73,7 +73,8 @@ int drkaiser_init(void) return 1; /* Write magic register to enable flash write. */ - rpci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE); + if (rpci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE)) + return 1; /* Map 128kB flash memory window. */ drkaiser_bar = rphysmap("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); diff --git a/gfxnvidia.c b/gfxnvidia.c index d3ee14e..582298d 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -103,7 +103,8 @@ int gfxnvidia_init(void) /* Allow access to flash interface (will disable screen). */ reg32 = pci_read_long(dev, 0x50); reg32 &= ~(1 << 0); - rpci_write_long(dev, 0x50, reg32); + if (rpci_write_long(dev, 0x50, reg32)) + return 1; /* Write/erase doesn't work. */ programmer_may_write = 0; diff --git a/pcidev.c b/pcidev.c index 3a3f77c..b3fdead 100644 --- a/pcidev.c +++ b/pcidev.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <string.h> +#include <errno.h> #include "flash.h" #include "programmer.h" #include "hwaccess.h" @@ -302,7 +303,7 @@ int undo_pci_write(void *p) undo_pci_write_data = malloc(sizeof(struct undo_pci_write_data)); \ if (!undo_pci_write_data) { \ msg_gerr("Out of memory!\n"); \ - exit(1); \ + return ENOMEM; \ } \ undo_pci_write_data->dev = *a; \ undo_pci_write_data->reg = b; \ @@ -318,17 +319,29 @@ int undo_pci_write(void *p) int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data) { register_undo_pci_write_byte(dev, reg); - return pci_write_byte(dev, reg, data); + if (pci_write_byte(dev, reg, data) != 1) { + msg_gerr("pci write byte failed\n"); + return 1; + } + return 0; } int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data) { register_undo_pci_write_word(dev, reg); - return pci_write_word(dev, reg, data); + if (pci_write_word(dev, reg, data) != 1) { + msg_gerr("pci write word failed\n"); + return 1; + } + return 0; } int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data) { register_undo_pci_write_long(dev, reg); - return pci_write_long(dev, reg, data); + if (pci_write_long(dev, reg, data) != 1) { + msg_gerr("pci write long failed\n"); + return 1; + } + return 0; } -- 1.8.3.4

1 1

[PATCH 1/5] rayer_spi: Improve support for different pinouts
by Kyösti Mälkki Oct. 1, 2013

Oct. 1, 2013

Create a list of programmer types with names. This list could be listed with flashrom -L in follow-up patches. Handle a bit in status register that is inverted, this will be used in different future programmer types. I did trivial change after receiving the Tested-by. Local variable storage is declared static and bit offset in register is uint8_t. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: Maksim Kuleshov <mmcx(a)mail.ru> Acked-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- rayer_spi.c | 106 ++++++++++++++++++++++++++++++++++-------------------------- 1 file changed, 61 insertions(+), 45 deletions(-) diff --git a/rayer_spi.c b/rayer_spi.c index b312610..cbbd5ce 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -37,21 +37,48 @@ #include "programmer.h" #include "hwaccess.h" -enum rayer_type { - TYPE_RAYER, - TYPE_XILINX_DLC5, -}; - /* We have two sets of pins, out and in. The numbers for both sets are * independent and are bitshift values, not real pin numbers. * Default settings are for the RayeR hardware. */ -/* Pins for master->slave direction */ -static int rayer_cs_bit = 5; -static int rayer_sck_bit = 6; -static int rayer_mosi_bit = 7; -/* Pins for slave->master direction */ -static int rayer_miso_bit = 6; + +struct rayer_programmer { + const char * type; + const enum test_state status; + const char * description; + const void * private; +}; + +struct rayer_pinout { + uint8_t cs_bit; + uint8_t sck_bit; + uint8_t mosi_bit; + uint8_t miso_bit; + void (*preinit)(void *); + int (*shutdown)(void *); +}; + +static struct rayer_pinout rayer_spipgm = { + .cs_bit = 5, + .sck_bit = 6, + .mosi_bit = 7, + .miso_bit = 6, +}; + +static struct rayer_pinout xilinx_dlc5 = { + .cs_bit = 2, + .sck_bit = 1, + .mosi_bit = 0, + .miso_bit = 4, +}; + +static struct rayer_programmer rayer_spi_types[] = { + {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm}, + {"xilinx", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5}, + {0}, +}; + +static struct rayer_pinout *pinout = NULL; static uint16_t lpt_iobase; @@ -60,22 +87,22 @@ static uint8_t lpt_outbyte; static void rayer_bitbang_set_cs(int val) { - lpt_outbyte &= ~(1 << rayer_cs_bit); - lpt_outbyte |= (val << rayer_cs_bit); + lpt_outbyte &= ~(1 << pinout->cs_bit); + lpt_outbyte |= (val << pinout->cs_bit); OUTB(lpt_outbyte, lpt_iobase); } static void rayer_bitbang_set_sck(int val) { - lpt_outbyte &= ~(1 << rayer_sck_bit); - lpt_outbyte |= (val << rayer_sck_bit); + lpt_outbyte &= ~(1 << pinout->sck_bit); + lpt_outbyte |= (val << pinout->sck_bit); OUTB(lpt_outbyte, lpt_iobase); } static void rayer_bitbang_set_mosi(int val) { - lpt_outbyte &= ~(1 << rayer_mosi_bit); - lpt_outbyte |= (val << rayer_mosi_bit); + lpt_outbyte &= ~(1 << pinout->mosi_bit); + lpt_outbyte |= (val << pinout->mosi_bit); OUTB(lpt_outbyte, lpt_iobase); } @@ -83,8 +110,8 @@ static int rayer_bitbang_get_miso(void) { uint8_t tmp; - tmp = INB(lpt_iobase + 1); - tmp = (tmp >> rayer_miso_bit) & 0x1; + tmp = INB(lpt_iobase + 1) ^ 0x80; // bit.7 inverted + tmp = (tmp >> pinout->miso_bit) & 0x1; return tmp; } @@ -99,8 +126,8 @@ static const struct bitbang_spi_master bitbang_spi_master_rayer = { int rayer_spi_init(void) { + struct rayer_programmer *prog = rayer_spi_types; char *arg = NULL; - enum rayer_type rayer_type = TYPE_RAYER; /* Non-default port requested? */ arg = extract_programmer_param("iobase"); @@ -138,36 +165,20 @@ int rayer_spi_init(void) arg = extract_programmer_param("type"); if (arg) { - if (!strcasecmp(arg, "rayer")) { - rayer_type = TYPE_RAYER; - } else if (!strcasecmp(arg, "xilinx")) { - rayer_type = TYPE_XILINX_DLC5; - } else { + for (; prog->type; ++prog) { + if (! strcasecmp (arg, prog->type)) { + break; + } + } + if(! prog->type) { msg_perr("Error: Invalid device type specified.\n"); free(arg); return 1; } + free(arg); } - free(arg); - switch (rayer_type) { - case TYPE_RAYER: - msg_pdbg("Using RayeR SPIPGM pinout.\n"); - /* Bits for master->slave direction */ - rayer_cs_bit = 5; - rayer_sck_bit = 6; - rayer_mosi_bit = 7; - /* Bits for slave->master direction */ - rayer_miso_bit = 6; - break; - case TYPE_XILINX_DLC5: - msg_pdbg("Using Xilinx Parallel Cable III (DLC 5) pinout.\n"); - /* Bits for master->slave direction */ - rayer_cs_bit = 2; - rayer_sck_bit = 1; - rayer_mosi_bit = 0; - /* Bits for slave->master direction */ - rayer_miso_bit = 4; - } + msg_pinfo("Using %s pinout.\n", prog->description); + pinout = (struct rayer_pinout *) prog->private; if (rget_io_perms()) return 1; @@ -175,6 +186,11 @@ int rayer_spi_init(void) /* Get the initial value before writing to any line. */ lpt_outbyte = INB(lpt_iobase); + if (pinout->shutdown) + register_shutdown(pinout->shutdown, (void*)pinout); + if (pinout->preinit) + pinout->preinit(pinout); + if (bitbang_spi_init(&bitbang_spi_master_rayer)) return 1; -- 1.8.1.1

4 12

[not working] Abit IS7 (P4)
by san Sept. 30, 2013

Sept. 30, 2013

Hi! I'm trying to run flashrom on my platform but no luck. All info, bios etc. are avalaible here: http://www.e-san.info/Go!/deeper!/Flashrom-Przemo/ but i'll attach it too (without bios). Best Regards! -- [ e-San.info | San(a)plusnet.pl ]

1 0

W836xx: ASUS A7N8X-X: flashrom -V
by Markas Sept. 29, 2013

Sept. 29, 2013

Greetings flashrom folks, Below is some hopefully helpful output. Many thanks, Mark flashrom v0.9.6.1-r1705 on Linux 3.9.5-301.fc19.i686 (i686) flashrom was built with libpci 3.2.0, GCC 4.8.1 20130603 (Red Hat 4.8.1-1), little endian Command line (3 args): flashrom -V -o flashrom.log Using default programmer "internal". Calibrating delay loop... OS timer resolution is 1 usecs, 958M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1005 us, 10000 myus = 15085 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "ASUSTeK Computer INC." DMI string system-product-name: "A7N8X-X" DMI string system-version: "REV 2.xx" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "A7N8X-X" DMI string baseboard-version: "REV 2.xx" DMI string chassis-type: "Desktop" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 87. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE Super I/O, ID 0x8708 on port 0x2e Found chipset "NVIDIA NForce2" with PCI ID 10de:0060. Enabling flash write... OK. Super I/O ID 0x8708 is not on the list of flash capable controllers. The following protocols are supported: Non-SPI. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0x66, id2 0x58, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0x66, id2 0x58, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0x66, id2 0x58, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT49(H)F010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT49F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT49F080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT49F080T, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for ESMT F49B002UA, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0x66, id2 0x58, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29LV640B, 8192 kB: probe_en29lv640b: id1 0x2589, id2 0x002d Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0x25, id2 0x2d, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0x25, id2 0x2d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0x66, id2 0x58, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0x66, id2 0x58, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0x66, id2 0x58, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV512, 64 kB: probe_jedec_common: id1 0xaa, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Found SST flash chip "SST49LF020" (256 kB, LPC) at physical address 0xfffc0000. Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x61 Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0x66, id2 0x58, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xaa, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0x25, id2 0x53, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39F010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39L010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39L020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x61 Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xbf, id2 0x61 Found SST flash chip "SST49LF020" (256 kB, LPC). No operations were specified. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x92

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test flashrom on Gigabyte GA-Z68MA-D2H-B3 (rev. 1.3) mainboard
by Vangelis Skarmoutsos Sept. 28, 2013

Sept. 28, 2013

The flashing succeeded. All worked perfect. Attachments: dump1 (flashrom -p internal -V) dump2 (lspci -nnvvxxx) dump3 (superiotool -deV) * * I would prefer if "-p internal" was the default (less typing). The tool is really easy to use but a GUI would be preferred. Thank you anyway for this wonderful tool.

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Donations in Bitcoin
by Fabián Rodríguez Sept. 28, 2013

Sept. 28, 2013

Hi, I am attending the GNU 30th anniversary hackathon/events and when I asked about donating in Bitcoin it was suggested I asked here. I'd like to make a donation, perhaps a project member can take it personally and then use it in the project. It would be nice to be able to donate on the site directly too. I prefer not to donate in cash in person as I need the currency for local use. Cheers, Fabian -- Fabián Rodríguez http://fsf.magicfab.ca

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