Change in flashrom[master]: chipset_enable.c: Add Intel pch6 pid=0x1e4{1,2,3} support

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47090 )

Change subject: chipset_enable.c: Add Intel pch6 pid=0x1e4{1,2,3} support
......................................................................

chipset_enable.c: Add Intel pch6 pid=0x1e4{1,2,3} support

BUG=none
BRANCH=none
TEST=none

Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447
Signed-off-by: Edward O'Callaghan 
---
M chipset_enable.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/47090/1

diff --git a/chipset_enable.c b/chipset_enable.c
index a0ac6c1..c664918 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1839,6 +1839,9 @@
    {0x8086, 0x1c5c, B_FS,   DEP, "Intel", "H61",				enable_flash_pch6},
    {0x8086, 0x1d40, B_FS,   DEP, "Intel", "C60x/X79",			enable_flash_pch6},
    {0x8086, 0x1d41, B_FS,   DEP, "Intel", "C60x/X79",			enable_flash_pch6},
+	{0x8086, 0x1e41, B_FS,   OK,  "Intel", "Desktop Full",			enable_flash_pch6},
+	{0x8086, 0x1e42, B_FS,   OK,  "Intel", "Mobile Full",			enable_flash_pch6},
+	{0x8086, 0x1e43, B_FS,   OK,  "Intel", "Mobile SFF",			enable_flash_pch6},
    {0x8086, 0x1e44, B_FS,   DEP, "Intel", "Z77",				enable_flash_pch7},
    {0x8086, 0x1e46, B_FS,   NT,  "Intel", "Z75",				enable_flash_pch7},
    {0x8086, 0x1e47, B_FS,   DEP, "Intel", "Q77",				enable_flash_pch7},