Nico Huber has posted comments on this change. ( https://review.coreboot.org/18925 )
Change subject: chipset_enable: Add support for Intel Skylake / Kabylake ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/18925/2/chipset_enable.c File chipset_enable.c:
Line 852: struct pci_dev *const spi_dev = pci_get_dev(pci_acc, 0, 0, 0x1f, 5);
It just confused me at first, rather than be recognizable, I guess I'd stil
It feels pretty common when you've looked too much at coreboot source.
Line 858: const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc);
Humm.. could it be by any chance the EC chip ? The librems have a separate
The EC flash can be anywhere, even shared SPI chips are possible. But usually, today, you have to ask the EC in a proprietary way to access its flash. One configuration that was common ~10 years ago: a shared SPI flash connected to the EC; the BIOS was then accessed over LPC through the EC ;) that's why we have that scary warning about flashing laptops.
The chromiumos patch didn't touch the LPC stuff too, IIRC.
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Nico Huber (Code Review)