Nico Huber has posted comments on this change. ( https://review.coreboot.org/28813 )
Change subject: flashchips: Add Sanyo LE25FU206/A and LE25FU106B ......................................................................
Patch Set 2:
(9 comments)
Needs many fixes and retesting I guess.
https://review.coreboot.org/#/c/28813/2/flashchips.h File flashchips.h:
https://review.coreboot.org/#/c/28813/2/flashchips.h@609 PS2, Line 609: 62 The chip doesn't support the three byte RDID, 0x62 is just the repetition of the vendor id.
https://review.coreboot.org/#/c/28813/2/flashchips.h@610 PS2, Line 610: #define SANYO_LE25FU206 0x4462 same here, I guess
https://review.coreboot.org/#/c/28813/2/flashchips.c File flashchips.c:
https://review.coreboot.org/#/c/28813/2/flashchips.c@11628 PS2, Line 11628: .probe = probe_spi_rdid, datasheet suggests res2
https://review.coreboot.org/#/c/28813/2/flashchips.c@11632 PS2, Line 11632: .eraseblocks = { {2 * 1024, 64} }, The datasheet I'm reading suggests 4KiB sectors... wrote a mail.
https://review.coreboot.org/#/c/28813/2/flashchips.c@11649 PS2, Line 11649: { missing tab
https://review.coreboot.org/#/c/28813/2/flashchips.c@11656 PS2, Line 11656: .page_size = 256, datasheet suggests WRSR_WREN
https://review.coreboot.org/#/c/28813/2/flashchips.c@11658 PS2, Line 11658: .probe = probe_spi_rdid, same here
https://review.coreboot.org/#/c/28813/2/flashchips.c@11673 PS2, Line 11673: .printlock = spi_prettyprint_status_register_bp2_srwd, : .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ Datasheet suggests the same register layout as for 106B?
https://review.coreboot.org/#/c/28813/2/flashchips.c@11685 PS2, Line 11685: .model_id = SANYO_LE25FU206A, Judging from the similarity to the 25FU406C id (0x0612 / 0x0613), We might also want to test the additional erase opcodes known for the 406C.
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Nico Huber (Code Review)