Change in flashrom[master]: tests/: Add spi25.c unit tests
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41645 ) Change subject: tests/: Add spi25.c unit tests ...................................................................... tests/: Add spi25.c unit tests Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Signed-off-by: Edward O'Callaghan <quasisec@google.com> --- M tests/meson.build A tests/spi25.c M tests/tests.c M tests/tests.h 4 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/45/41645/1 diff --git a/tests/meson.build b/tests/meson.build index 5af0a3e..3ed1c3b 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -3,11 +3,13 @@ srcs = [ 'tests.c', 'spi.c', + 'spi25.c', ] mocks = [ '-Wl,--wrap=physunmap', '-Wl,--wrap=physmap', + '-Wl,--wrap=spi_send_command', '-Wl,--gc-sections', ] diff --git a/tests/spi25.c b/tests/spi25.c new file mode 100644 index 0000000..cf8345c --- /dev/null +++ b/tests/spi25.c @@ -0,0 +1,170 @@ +#include <include/test.h> + +#include "programmer.h" +#include "flashchips.h" +#include "chipdrivers.h" +#include "spi.h" + +int __wrap_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + check_expected_ptr(flash); + assert_int_equal(writecnt, mock_type(int)); + assert_int_equal(writearr[0], mock_type(int)); + + int rcnt = mock_type(int); + assert_int_equal(readcnt, rcnt); + for (int i = 0; i < rcnt; i++) + readarr[i] = i; + + return 0; +} + +struct flashchip mock_chip = { + .vendor = "Generic", + .name = "unknown SPI chip (RDID)", + .bustype = BUS_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rdid, + .write = NULL, +}; + +void spi_write_enable_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_WREN_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_WREN); + will_return(__wrap_spi_send_command, JEDEC_WREN_INSIZE); + assert_int_equal(0, spi_write_enable(&flashctx)); +} + +void spi_write_disable_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_WRDI_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_WRDI); + will_return(__wrap_spi_send_command, JEDEC_WRDI_INSIZE); + assert_int_equal(0, spi_write_disable(&flashctx)); +} + +void probe_spi_rdid_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RDID_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RDID); + will_return(__wrap_spi_send_command, JEDEC_RDID_INSIZE); + assert_int_equal(0, probe_spi_rdid(&flashctx)); +} + +void probe_spi_rdid4_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RDID_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RDID); + will_return(__wrap_spi_send_command, JEDEC_RDID_INSIZE + 1); + assert_int_equal(0, probe_spi_rdid4(&flashctx)); +} + +void probe_spi_rems_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_REMS_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_REMS); + will_return(__wrap_spi_send_command, JEDEC_REMS_INSIZE); + assert_int_equal(0, probe_spi_rems(&flashctx)); +} + +void probe_spi_res1_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RES_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RES); + will_return(__wrap_spi_send_command, JEDEC_RES_INSIZE + 1); + assert_int_equal(0, probe_spi_res2(&flashctx)); +} + +void probe_spi_res2_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RES_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RES); + will_return(__wrap_spi_send_command, JEDEC_RES_INSIZE + 1); + assert_int_equal(0, probe_spi_res2(&flashctx)); +} + +void probe_spi_res3_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RES_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RES); + will_return(__wrap_spi_send_command, JEDEC_RES_INSIZE + 2); + assert_int_equal(0, probe_spi_res3(&flashctx)); +} + +void probe_spi_at25f_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, AT25F_RDID_OUTSIZE); + will_return(__wrap_spi_send_command, AT25F_RDID); + will_return(__wrap_spi_send_command, AT25F_RDID_INSIZE); + assert_int_equal(0, probe_spi_at25f(&flashctx)); +} diff --git a/tests/tests.c b/tests/tests.c index 338646e..16f4863 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -24,5 +24,18 @@ }; ret |= cmocka_run_group_tests_name("spi.c tests", spi_tests, NULL, NULL); + const struct CMUnitTest spi25_tests[] = { + cmocka_unit_test(spi_write_enable_test_success), + cmocka_unit_test(spi_write_disable_test_success), + cmocka_unit_test(probe_spi_rdid_test_success), + cmocka_unit_test(probe_spi_rdid4_test_success), + cmocka_unit_test(probe_spi_rems_test_success), + cmocka_unit_test(probe_spi_res1_test_success), + cmocka_unit_test(probe_spi_res2_test_success), + cmocka_unit_test(probe_spi_res3_test_success), + cmocka_unit_test(probe_spi_at25f_test_success), + }; + ret |= cmocka_run_group_tests_name("spi25.c tests", spi25_tests, NULL, NULL); + return ret; } diff --git a/tests/tests.h b/tests/tests.h index ccc3f5e..9377817 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -4,4 +4,15 @@ void registered_masters_test_success(void **state); void programmer_init_test_success(void **state); +/* spi25.c */ +void spi_write_enable_test_success(void **state); +void spi_write_disable_test_success(void **state); +void probe_spi_rdid_test_success(void **state); +void probe_spi_rdid4_test_success(void **state); +void probe_spi_rems_test_success(void **state); +void probe_spi_res1_test_success(void **state); +void probe_spi_res2_test_success(void **state); +void probe_spi_res3_test_success(void **state); +void probe_spi_at25f_test_success(void **state); + #endif /* TESTS_H */ -- To view, visit https://review.coreboot.org/c/flashrom/+/41645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Gerrit-Change-Number: 41645 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org> Gerrit-MessageType: newchange
Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/41645 to look at the new patch set (#2). Change subject: tests/: Add spi25.c unit tests ...................................................................... tests/: Add spi25.c unit tests BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Signed-off-by: Edward O'Callaghan <quasisec@google.com> --- M tests/meson.build A tests/spi25.c M tests/tests.c M tests/tests.h 4 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/45/41645/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/41645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Gerrit-Change-Number: 41645 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-MessageType: newpatchset
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/41645 ) Change subject: tests/: Add spi25.c unit tests ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/flashrom/+/41645/2/tests/spi25.c File tests/spi25.c: https://review.coreboot.org/c/flashrom/+/41645/2/tests/spi25.c@17 PS2, Line 17: I guess those spaces aren't needed anymore -- To view, visit https://review.coreboot.org/c/flashrom/+/41645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Gerrit-Change-Number: 41645 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-Comment-Date: Fri, 22 May 2020 12:41:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/41645 ) Change subject: tests/: Add spi25.c unit tests ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/flashrom/+/41645/2/tests/spi25.c File tests/spi25.c: https://review.coreboot.org/c/flashrom/+/41645/2/tests/spi25.c@17 PS2, Line 17:
I guess those spaces aren't needed anymore Done
-- To view, visit https://review.coreboot.org/c/flashrom/+/41645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Gerrit-Change-Number: 41645 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-Comment-Date: Fri, 22 May 2020 14:51:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus@gmail.com> Gerrit-MessageType: comment
Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/41645 to look at the new patch set (#3). Change subject: tests/: Add spi25.c unit tests ...................................................................... tests/: Add spi25.c unit tests BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Signed-off-by: Edward O'Callaghan <quasisec@google.com> --- M tests/meson.build A tests/spi25.c M tests/tests.c M tests/tests.h 4 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/45/41645/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/41645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Gerrit-Change-Number: 41645 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-MessageType: newpatchset
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/41645 ) Change subject: tests/: Add spi25.c unit tests ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/41645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Gerrit-Change-Number: 41645 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer@coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-Comment-Date: Tue, 16 Jun 2020 02:12:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/41645 ) Change subject: tests/: Add spi25.c unit tests ...................................................................... tests/: Add spi25.c unit tests BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> --- M tests/meson.build A tests/spi25.c M tests/tests.c M tests/tests.h 4 files changed, 196 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/tests/meson.build b/tests/meson.build index 0c21cb9..76088c2 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -2,11 +2,13 @@ srcs = [ 'tests.c', + 'spi25.c', ] mocks = [ '-Wl,--wrap=physunmap', '-Wl,--wrap=physmap', + '-Wl,--wrap=spi_send_command', '-Wl,--gc-sections', ] diff --git a/tests/spi25.c b/tests/spi25.c new file mode 100644 index 0000000..9932574 --- /dev/null +++ b/tests/spi25.c @@ -0,0 +1,170 @@ +#include <include/test.h> + +#include "programmer.h" +#include "flashchips.h" +#include "chipdrivers.h" +#include "spi.h" + +int __wrap_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + check_expected_ptr(flash); + assert_int_equal(writecnt, mock_type(int)); + assert_int_equal(writearr[0], mock_type(int)); + + int rcnt = mock_type(int); + assert_int_equal(readcnt, rcnt); + for (int i = 0; i < rcnt; i++) + readarr[i] = i; + + return 0; +} + +struct flashchip mock_chip = { + .vendor = "Generic", + .name = "unknown SPI chip (RDID)", + .bustype = BUS_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rdid, + .write = NULL, +}; + +void spi_write_enable_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_WREN_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_WREN); + will_return(__wrap_spi_send_command, JEDEC_WREN_INSIZE); + assert_int_equal(0, spi_write_enable(&flashctx)); +} + +void spi_write_disable_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_WRDI_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_WRDI); + will_return(__wrap_spi_send_command, JEDEC_WRDI_INSIZE); + assert_int_equal(0, spi_write_disable(&flashctx)); +} + +void probe_spi_rdid_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RDID_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RDID); + will_return(__wrap_spi_send_command, JEDEC_RDID_INSIZE); + assert_int_equal(0, probe_spi_rdid(&flashctx)); +} + +void probe_spi_rdid4_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RDID_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RDID); + will_return(__wrap_spi_send_command, JEDEC_RDID_INSIZE + 1); + assert_int_equal(0, probe_spi_rdid4(&flashctx)); +} + +void probe_spi_rems_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_REMS_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_REMS); + will_return(__wrap_spi_send_command, JEDEC_REMS_INSIZE); + assert_int_equal(0, probe_spi_rems(&flashctx)); +} + +void probe_spi_res1_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RES_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RES); + will_return(__wrap_spi_send_command, JEDEC_RES_INSIZE + 1); + assert_int_equal(0, probe_spi_res2(&flashctx)); +} + +void probe_spi_res2_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RES_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RES); + will_return(__wrap_spi_send_command, JEDEC_RES_INSIZE + 1); + assert_int_equal(0, probe_spi_res2(&flashctx)); +} + +void probe_spi_res3_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RES_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RES); + will_return(__wrap_spi_send_command, JEDEC_RES_INSIZE + 2); + assert_int_equal(0, probe_spi_res3(&flashctx)); +} + +void probe_spi_at25f_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, AT25F_RDID_OUTSIZE); + will_return(__wrap_spi_send_command, AT25F_RDID); + will_return(__wrap_spi_send_command, AT25F_RDID_INSIZE); + assert_int_equal(0, probe_spi_at25f(&flashctx)); +} diff --git a/tests/tests.c b/tests/tests.c index 32353fa..82563ac 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -21,5 +21,18 @@ { int ret = 0; + const struct CMUnitTest spi25_tests[] = { + cmocka_unit_test(spi_write_enable_test_success), + cmocka_unit_test(spi_write_disable_test_success), + cmocka_unit_test(probe_spi_rdid_test_success), + cmocka_unit_test(probe_spi_rdid4_test_success), + cmocka_unit_test(probe_spi_rems_test_success), + cmocka_unit_test(probe_spi_res1_test_success), + cmocka_unit_test(probe_spi_res2_test_success), + cmocka_unit_test(probe_spi_res3_test_success), + cmocka_unit_test(probe_spi_at25f_test_success), + }; + ret |= cmocka_run_group_tests_name("spi25.c tests", spi25_tests, NULL, NULL); + return ret; } diff --git a/tests/tests.h b/tests/tests.h index b088e24..6eafeea 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -1,4 +1,15 @@ #ifndef TESTS_H #define TESTS_H +/* spi25.c */ +void spi_write_enable_test_success(void **state); +void spi_write_disable_test_success(void **state); +void probe_spi_rdid_test_success(void **state); +void probe_spi_rdid4_test_success(void **state); +void probe_spi_rems_test_success(void **state); +void probe_spi_res1_test_success(void **state); +void probe_spi_res2_test_success(void **state); +void probe_spi_res3_test_success(void **state); +void probe_spi_at25f_test_success(void **state); + #endif /* TESTS_H */ -- To view, visit https://review.coreboot.org/c/flashrom/+/41645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Gerrit-Change-Number: 41645 Gerrit-PatchSet: 5 Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer@coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-MessageType: merged
participants (3)
-
Angel Pons (Code Review) -
Edward O'Callaghan (Code Review)
-
Stefan Reinauer (Code Review)