Change in flashrom[staging]: spi25: Use common code for nbyte read/write and erase

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/22019 )

Change subject: spi25: Use common code for nbyte read/write and erase
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Patch Set 1: Code-Review-1

(6 comments)

Mostly looks good, just a few minor things.

https://review.coreboot.org/#/c/22019/1//COMMIT_MSG
Commit Message:

https://review.coreboot.org/#/c/22019/1//COMMIT_MSG@9
PS1, Line 9: spi_write_command
spi_write_cmd


https://review.coreboot.org/#/c/22019/1//COMMIT_MSG@10
PS1, Line 10: erase
block erase, since it doesn't apply to chip erase functions


https://review.coreboot.org/#/c/22019/1//COMMIT_MSG@12
PS1, Line 12: spi_write_command
spi_write_cmd


https://review.coreboot.org/#/c/22019/1/spi25.c
File spi25.c:

https://review.coreboot.org/#/c/22019/1/spi25.c@326
PS1, Line 326: spi_write_status
spi_poll_status?


https://review.coreboot.org/#/c/22019/1/spi25.c@377
PS1, Line 377: JEDEC_WREN 
Hmmm, what do we do about chips that only use EWSR? I know this patch is only intended to
replace the old functions, but maybe in a follow-up we can add some logic to check the
feature bits to see which enable opcode we should use.


https://review.coreboot.org/#/c/22019/1/spi25.c@383
PS1, Line 383: 
Check if out_len < 1?



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Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-MessageType: comment
Gerrit-Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503
Gerrit-Change-Number: 22019
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber &lt;nico.h(a)gmx.de&gt;
Gerrit-Reviewer: David Hendricks &lt;david.hendricks(a)gmail.com&gt;
Gerrit-Reviewer: build bot (Jenkins) &lt;no-reply(a)coreboot.org&gt;
Gerrit-Comment-Date: Tue, 17 Oct 2017 00:24:32 +0000
Gerrit-HasComments: Yes