Change in flashrom[master]: flashchips: Add W25Q128JW_DTR

[Peichao Li (Code Review)]

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

flashchips: Add W25Q128JW_DTR

Port the code from chromeos flashrom.
Tested using W25Q128JWDTR in SPI mode.

Signed-off-by: Peichao.Wang 
Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e
---
M flashchips.c
M flashchips.h
2 files changed, 39 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/36717/1

diff --git a/flashchips.c b/flashchips.c
index 517289a..4324c11 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -16414,6 +16414,44 @@

{
    	.vendor		= "Winbond",
+		.name		= "W25Q128.JW.DTR",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= WINBOND_NEX_ID,
+		.model_id	= WINBOND_NEX_W25Q128_DTR,
+		.total_size	= 16384,
+		.page_size	= 256,
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+		.tested		= TEST_OK_PREW,
+		.probe		= probe_spi_rdid,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 4096} },
+				.block_erase = spi_block_erase_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 512} },
+				.block_erase = spi_block_erase_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 256} },
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_60,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.printlock      = spi_prettyprint_status_register_plain, /* TODO: improve */
+		.unlock		= spi_disable_blockprotect,
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+		.voltage	= {1650, 1950},
+	},
+
+	{
+		.vendor		= "Winbond",
    	.name		= "W25Q16.V",
    	.bustype	= BUS_SPI,
    	.manufacture_id	= WINBOND_NEX_ID,
diff --git a/flashchips.h b/flashchips.h
index 5ef7f9c..2c2da6c 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -939,6 +939,7 @@
 #define WINBOND_NEX_W25Q128_W	0x6018	/* W25Q128FW; W25Q128FV in QPI mode */
 #define WINBOND_NEX_W25Q128_V_M	0x7018	/* W25Q128JVSM */
 #define WINBOND_NEX_W25Q256JV_M	0x7019	/* W25Q256JV_M (QE=0) */
+#define WINBOND_NEX_W25Q128_DTR	0x8018	/* W25Q128JW_DTR */

#define WINBOND_ID		0xDA	/* Winbond */
 #define WINBOND_W19B160BB	0x49

[Peichao Li (Code Review)]

Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/36717

to look at the new patch set (#2).

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

flashchips: Add W25Q128JW_DTR

Port the code from chromeos flashrom

BUG=None
TEST=Tested using W25Q128JWDTR in SPI mode

Signed-off-by: Peichao.Wang 
Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e
---
M flashchips.c
M flashchips.h
2 files changed, 39 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/36717/2

[Peichao Li (Code Review)]

Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/36717

to look at the new patch set (#3).

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

flashchips: Add W25Q128JW_DTR

Port the code from chromeos flashrom

BUG=b:144297264
TEST=Tested using W25Q128JWDTR in SPI mode

Signed-off-by: Peichao.Wang 
Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e
---
M flashchips.c
M flashchips.h
2 files changed, 39 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/36717/3

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c@16424 
PS3, Line 16424: TEST_OK_PREW
Did you test all the operations here?

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

Patch Set 3: Code-Review+1

(1 comment)

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c@16424 
PS3, Line 16424: TEST_OK_PREW
> Did you test all the operations here?

In the ChromeOS flashrom tree under utils there is a program called flashrom_tester you can use to verify all the operations work. It comes by default as part of the test image.

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

Patch Set 3: Code-Review+2
> Patch Set 3: Code-Review+1
>
> (1 comment)

Thanks for testing with me.

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c@16424 
PS3, Line 16424: TEST_OK_PREW
> In the ChromeOS flashrom tree under utils there is a program called flashrom_tester you can use to v […]

Done

[Peichao Li (Code Review)]

Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

Patch Set 3:

(1 comment)
> Patch Set 3: Code-Review+1
>
> (1 comment)

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c@16424 
PS3, Line 16424: TEST_OK_PREW
> Done

Done

[Peichao Li (Code Review)]

Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/36717/3/flashchips.c@16424 
PS3, Line 16424: TEST_OK_PREW
> Done

Done

[Peichao Li (Code Review)]

Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

Patch Set 3:

Dear Patrick,

Could you kindly help merge it?

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

Patch Set 3:

Nico, any objections to getting this in? Looks harmless enough to me

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

Patch Set 3:

(1 comment)
> Nico, any objections to getting this in? Looks harmless enough to me

No objections. A candidate for the fastest flashrom merge ever? ^^

https://review.coreboot.org/c/flashrom/+/36717/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/36717/3//COMMIT_MSG@11 
PS3, Line 11: BUG=b:144297264
Not a fan of private references. In the coreboot project, this has
often led to confusion and fruitless discussions.

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/36717 )

Change subject: flashchips: Add W25Q128JW_DTR
......................................................................

flashchips: Add W25Q128JW_DTR

Port the code from chromeos flashrom

BUG=b:144297264
TEST=Tested using W25Q128JWDTR in SPI mode

Signed-off-by: Peichao.Wang 
Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36717
Reviewed-by: Edward O'Callaghan 
Tested-by: build bot (Jenkins) 
---
M flashchips.c
M flashchips.h
2 files changed, 39 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Edward O'Callaghan: Looks good to me, approved

diff --git a/flashchips.c b/flashchips.c
index 517289a..4324c11 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -16414,6 +16414,44 @@

{
    	.vendor		= "Winbond",
+		.name		= "W25Q128.JW.DTR",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= WINBOND_NEX_ID,
+		.model_id	= WINBOND_NEX_W25Q128_DTR,
+		.total_size	= 16384,
+		.page_size	= 256,
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+		.tested		= TEST_OK_PREW,
+		.probe		= probe_spi_rdid,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 4096} },
+				.block_erase = spi_block_erase_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 512} },
+				.block_erase = spi_block_erase_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 256} },
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_60,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.printlock      = spi_prettyprint_status_register_plain, /* TODO: improve */
+		.unlock		= spi_disable_blockprotect,
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+		.voltage	= {1650, 1950},
+	},
+
+	{
+		.vendor		= "Winbond",
    	.name		= "W25Q16.V",
    	.bustype	= BUS_SPI,
    	.manufacture_id	= WINBOND_NEX_ID,
diff --git a/flashchips.h b/flashchips.h
index 5ef7f9c..2c2da6c 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -939,6 +939,7 @@
 #define WINBOND_NEX_W25Q128_W	0x6018	/* W25Q128FW; W25Q128FV in QPI mode */
 #define WINBOND_NEX_W25Q128_V_M	0x7018	/* W25Q128JVSM */
 #define WINBOND_NEX_W25Q256JV_M	0x7019	/* W25Q256JV_M (QE=0) */
+#define WINBOND_NEX_W25Q128_DTR	0x8018	/* W25Q128JW_DTR */

#define WINBOND_ID		0xDA	/* Winbond */
 #define WINBOND_W19B160BB	0x49