zapb has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48380 )
Change subject: jlink_spi: Add option to enable target power ......................................................................
jlink_spi: Add option to enable target power
Change-Id: I026c22ae1c22541d0024f164c827909ca4a34cf4 Signed-off-by: Marc Schink dev@zapb.de --- M flashrom.8.tmpl M jlink_spi.c 2 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/48380/1
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index db50d59..2299dad 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -1279,6 +1279,9 @@ .sp syntax where \fBfrequency\fP is the SPI clock frequency in kHz. The maximum speed depends on the device in use. +.sp +The \fBpower=on\fP option can be used to activate the 5 V power supply (PWR_5V) +of the J-Link during a flash operation. .SS .BR "stlinkv3_spi " programmer .IP diff --git a/jlink_spi.c b/jlink_spi.c index 3a73c01..8344af2 100644 --- a/jlink_spi.c +++ b/jlink_spi.c @@ -54,6 +54,7 @@ static struct jaylink_context *jaylink_ctx; static struct jaylink_device_handle *jaylink_devh; static bool reset_cs; +static bool enable_target_power;
static bool assert_cs(void) { @@ -166,6 +167,15 @@
static int jlink_spi_shutdown(void *data) { + if (enable_target_power) { + int ret = jaylink_set_target_power(jaylink_devh, false); + + if (ret != JAYLINK_OK) { + msg_perr("jaylink_set_target_power() failed: %s.\n", + jaylink_strerror(ret)); + } + } + if (jaylink_devh) jaylink_close(jaylink_devh);
@@ -258,6 +268,21 @@ else msg_pdbg("Using TRST as chip select signal.\n");
+ enable_target_power = false; + arg = extract_programmer_param("power"); + + if (arg) { + if (!strcasecmp(arg, "on")) { + enable_target_power = true; + } else { + msg_perr("Invalid value for 'power' argument: '%s'.\n", arg); + free(arg); + return 1; + } + } + + free(arg); + ret = jaylink_init(&jaylink_ctx);
if (ret != JAYLINK_OK) { @@ -368,6 +393,13 @@ } }
+ if (enable_target_power) { + if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SET_TARGET_POWER)) { + msg_perr("Device does not support target power.\n"); + return 1; + } + } + uint32_t ifaces;
ret = jaylink_get_available_interfaces(jaylink_devh, &ifaces); @@ -389,6 +421,18 @@ return 1; }
+ if (enable_target_power) { + ret = jaylink_set_target_power(jaylink_devh, true); + + if (ret != JAYLINK_OK) { + msg_perr("jaylink_set_target_power() failed: %s.\n", jaylink_strerror(ret)); + return 1; + } + + /* Wait some time until the target is powered up. */ + internal_sleep(10000UL); + } + struct jaylink_hardware_status hwstat;
ret = jaylink_get_hardware_status(jaylink_devh, &hwstat);
Attention is currently required from: zapb. Miklós Márton has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48380 )
Change subject: jlink_spi: Add option to enable target power ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1: LGTM
Attention is currently required from: zapb. Hello build bot (Jenkins), Nico Huber, Miklós Márton,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/48380
to look at the new patch set (#2).
Change subject: jlink_spi: Add option to enable target power ......................................................................
jlink_spi: Add option to enable target power
Change-Id: I026c22ae1c22541d0024f164c827909ca4a34cf4 Signed-off-by: Marc Schink dev@zapb.de --- M flashrom.8.tmpl M jlink_spi.c 2 files changed, 50 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/48380/2
Attention is currently required from: zapb. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48380 )
Change subject: jlink_spi: Add option to enable target power ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File jlink_spi.c:
https://review.coreboot.org/c/flashrom/+/48380/comment/4a3b49a4_950cc6ce PS2, Line 443: UL Nit, specifying the type here won't make a difference (and doesn't match the signature either).
Attention is currently required from: zapb. Hello build bot (Jenkins), Nico Huber, Miklós Márton,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/48380
to look at the new patch set (#3).
Change subject: jlink_spi: Add option to enable target power ......................................................................
jlink_spi: Add option to enable target power
Change-Id: I026c22ae1c22541d0024f164c827909ca4a34cf4 Signed-off-by: Marc Schink dev@zapb.de --- M flashrom.8.tmpl M jlink_spi.c 2 files changed, 50 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/48380/3
Attention is currently required from: Nico Huber. zapb has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48380 )
Change subject: jlink_spi: Add option to enable target power ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File jlink_spi.c:
https://review.coreboot.org/c/flashrom/+/48380/comment/96f18371_0f54bc5c PS2, Line 443: UL
Nit, specifying the type here won't make a difference (and doesn't match […]
Correct :)
Attention is currently required from: zapb. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48380 )
Change subject: jlink_spi: Add option to enable target power ......................................................................
Patch Set 4: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/48380 )
Change subject: jlink_spi: Add option to enable target power ......................................................................
jlink_spi: Add option to enable target power
Change-Id: I026c22ae1c22541d0024f164c827909ca4a34cf4 Signed-off-by: Marc Schink dev@zapb.de Reviewed-on: https://review.coreboot.org/c/flashrom/+/48380 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M flashrom.8.tmpl M jlink_spi.c 2 files changed, 50 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved zapb: Looks good to me, but someone else must approve
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index db6d619..23b6f71 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -1422,6 +1422,9 @@ .sp syntax where \fBfrequency\fP is the SPI clock frequency in kHz. The maximum speed depends on the device in use. +.sp +The \fBpower=on\fP option can be used to activate the 5 V power supply (PWR_5V) +of the J-Link during a flash operation. .SS .BR "stlinkv3_spi " programmer .IP diff --git a/jlink_spi.c b/jlink_spi.c index 4b34bfd..65084b4 100644 --- a/jlink_spi.c +++ b/jlink_spi.c @@ -55,6 +55,7 @@ struct jaylink_context *ctx; struct jaylink_device_handle *devh; bool reset_cs; + bool enable_target_power; };
static bool assert_cs(struct jlink_spi_data *jlink_data) @@ -158,11 +159,20 @@ static int jlink_spi_shutdown(void *data) { struct jlink_spi_data *jlink_data = data; + + if (jlink_data->enable_target_power) { + int ret = jaylink_set_target_power(jlink_data->devh, false); + + if (ret != JAYLINK_OK) { + msg_perr("jaylink_set_target_power() failed: %s.\n", + jaylink_strerror(ret)); + } + } + if (jlink_data->devh) jaylink_close(jlink_data->devh);
jaylink_exit(jlink_data->ctx); - /* jlink_data->ctx, jlink_data->devh are freed by jaylink_close and jaylink_exit */ free(jlink_data); return 0; @@ -190,6 +200,7 @@ struct jaylink_device_handle *jaylink_devh = NULL; bool reset_cs; struct jlink_spi_data *jlink_data = NULL; + bool enable_target_power;
arg = extract_programmer_param("spispeed");
@@ -268,6 +279,21 @@ else msg_pdbg("Using TRST as chip select signal.\n");
+ enable_target_power = false; + arg = extract_programmer_param("power"); + + if (arg) { + if (!strcasecmp(arg, "on")) { + enable_target_power = true; + } else { + msg_perr("Invalid value for 'power' argument: '%s'.\n", arg); + free(arg); + return 1; + } + } + + free(arg); + ret = jaylink_init(&jaylink_ctx);
if (ret != JAYLINK_OK) { @@ -377,6 +403,13 @@ } }
+ if (enable_target_power) { + if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SET_TARGET_POWER)) { + msg_perr("Device does not support target power.\n"); + goto init_err; + } + } + uint32_t ifaces;
ret = jaylink_get_available_interfaces(jaylink_devh, &ifaces); @@ -398,6 +431,18 @@ goto init_err; }
+ if (enable_target_power) { + ret = jaylink_set_target_power(jaylink_devh, true); + + if (ret != JAYLINK_OK) { + msg_perr("jaylink_set_target_power() failed: %s.\n", jaylink_strerror(ret)); + goto init_err; + } + + /* Wait some time until the target is powered up. */ + internal_sleep(10000); + } + struct jaylink_hardware_status hwstat;
ret = jaylink_get_hardware_status(jaylink_devh, &hwstat); @@ -464,6 +509,7 @@ jlink_data->ctx = jaylink_ctx; jlink_data->devh = jaylink_devh; jlink_data->reset_cs = reset_cs; + jlink_data->enable_target_power = enable_target_power;
/* Ensure that the CS signal is not active initially. */ if (!deassert_cs(jlink_data))
-
Miklós Márton (Code Review) -
Nico Huber (Code Review)
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zapb (Code Review)