Attention is currently required from: Nico Huber, Subrata Banik, Caveh Jalali, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Angel Pons, Nick Vaccaro, Alex Levin, YH Lin, Boris Mittelberg.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/2e18981e_edabd184
PS2, Line 23: BUG=b:215255210
I have added the issue description below @Nico. […]
Ack
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/61854/comment/87be0750_23c1aa86
PS1, Line 1390: REGREAD32
Isn't this register 16-bit? […]
Ack
https://review.coreboot.org/c/flashrom/+/61854/comment/e7ce3e1a_33238220
PS1, Line 1392: } while ((hsfsts & HSFS_SCIP) == HSFS_SCIP);
This loop could potentially never exit.
It depends on HW operation and here is what EDS says, so, I believe we might not run into such issue. Also, *Software must only program the next command when this bit is 0.*
SPI Cycle In Progress (H_SCIP): Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register.
This bit remains set until the cycle completes on the SPI interface. Hardware
automatically sets and clears this bit so that software can determine when read data
is valid and/or when it is safe to begin programming the next command.
Software must only program the next command when this bit is 0.
This will ensure synchronisation in operations while using flashrom concurrently.
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